ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 106

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

ADE7169F16
Table 101. Timer 2 High byte SFR (TH2, 0xCD)
Bit Location
Table 102. Timer 2 Low byte SFR (TL2, 0xCC)
Bit Location
Table 103. Timer 2 Reload/capture High byte SFR (RACP2H, 0xCB)
Bit Location
Table 104. Timer 2 Reload/capture Low byte SFR (RACP2L, 0xCA)
Bit Location
TIMER 0 AND TIMER 1
Timer/Counter 0 and 1 Data Registers
Each timer consists of two 8-bit registers: Timer 0 High byte
SFR (TH0, 0x8C), Timer 0 Low byte SFR (TL0, 0x8A), Timer 1
High byte SFR (TH1, 0x8D) and Timer 1 Low byte SFR (TL1,
0x8B) These can be used as independent registers or combined
into a single 16-bit register, depending on the timers’ mode
configuration – see Table 97 to Table 100.
Timer/Counter 0 and 1 Operating Modes
This section describes the operating modes for Timer/Counters
0 and 1. Unless otherwise noted, these modes of operation are
the same for both Timer 0 and Timer 1.
Mode 0 (13-Bit Timer/Counter)
Mode 0 configures an 8-bit timer/counter. Figure 69 shows
Mode 0 operation. Note that the divide-by-12 prescaler is not
present on the single-cycle core.
In this mode, the timer register is configured as a 13-bit register.
P0.6/T0
F
CORE
GATE
7-0
7-0
7-0
7-0
INT0
TR0
Bit Mnemonic
TH2
Bit Mnemonic
TL2
Bit Mnemonic
TH2
Bit Mnemonic
TL2
Figure 69. Timer/Counter 0, Mode 0
C/T = 0
C/T = 1
CONTROL
(5 BITS)
TL0
(8 BITS)
TH0
Default
Default
Default
0
Default
0
Value
0
Value
0
Value
Value
TF0
Description
Timer 2 Data high byte
Description
Timer 2 Data high byte
Description
Timer 2 Reload/capture high byte
Description
Timer 2 Reload/capture low byte
INTERRUPT
Rev. PrD | Page 106 of 140
As the count rolls over from all 1s to all 0s, it sets the timer
overflow flag, TF0. TF0 can then be used to request an
interrupt. The counted input is enabled to the timer when TR0
= 1 and either Gate = 0 or INT0 = 1. Setting Gate = 1 allows the
timer to be controlled by external input INT0 to facilitate pulse-
width measurements. TR0 is a control bit in the Timer/Counter
0 and 1 Control SFR (TCON, 0x88); the Gate bit is in
Timer/Counter 0 and 1 Mode SFR (TMOD, 0x89). The 13-bit
register consists of all 8 bits of Timer 0 High byte SFR (TH0,
0x8C) and the lower 5 bits of Timer 0 Low byte SFR (TL0,
0x8A). The upper 3 bits of Timer 0 Low byte SFR (TL0, 0x8A)
are indeterminate and should be ignored. Setting the run flag
(TR0) does not clear the registers.
Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0 except that the Mode 1 timer
register runs with all 16 bits. Mode 1 is shown in Figure 70.
P0.6/T0
F
CORE
GATE
INT
0
TR0
Figure 70. Timer/Counter 0, Mode 1
C/T = 0
C/T = 1
Preliminary Technical Data
CONTROL
(8 BITS)
TL0
(8 BITS)
TH0
TF0
INTERRUPT