mc68hc908gr16 Freescale Semiconductor, Inc, mc68hc908gr16 Datasheet - Page 185

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mc68hc908gr16

Manufacturer Part Number
mc68hc908gr16
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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15.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume.
interrupt entry timing.
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared). See
Freescale Semiconductor
MODULE INTERRUPT
I BIT
INTERRUPT
R/W
I BIT
IDB
R/W
IAB
IDB
IAB
MODULE
DUMMY
DUMMY
Figure 15-10
SP – 4
SP
PC – 1[7:0] PC – 1[15:8]
CCR
Figure 15-10. Interrupt Recovery Timing
Figure 15-9
SP – 3
SP – 1
MC68HC908GR16 Data Sheet, Rev. 5.0
shows interrupt recovery timing.
A
SP – 2
SP – 2
.
Interrupt Entry Timing
X
X
Figure
SP – 1
SP – 3
PC – 1 [7:0] PC – 1 [15:8] OPCODE
15-11.
A
SP – 4
SP
CCR
VECT H
PC
V DATA H
PC + 1
VECT L
OPERAND
V DATA L
Figure 15-9
START ADDR
OPCODE
Exception Control
shows
185

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