mc68hc908gr16 Freescale Semiconductor, Inc, mc68hc908gr16 Datasheet - Page 248

• Manufacturer Part Number: mc68hc908gr16
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Development Support
19.3.1.5 Break Signal
A start bit (0) followed by nine 0 bits is a break signal. When the monitor receives a break signal, it drives
the PTA0 pin high for the duration of two bits and then echoes back the break signal.
19.3.1.6 Baud Rate
The communication baud rate is controlled by the crystal frequency or external clock and the state of the
PTB4 pin (when IRQ is set to V
on IRQ and the reset vector blank, then the baud rate is independent of PTB4.
Table 19-1
effective baud rate is the bus frequency divided by 256. If using a crystal as the clock source, be aware
of the upper frequency limit that the internal clock module can handle. See
or
19.3.1.7 Commands
The monitor ROM firmware uses these commands:
The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit
delay at the end of each command allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned.
The data returned by a read command appears after the echo of the last byte of the command.
248
20.8 3.3-Volt Control Timing
•
•
•
•
•
•
READ (read memory)
WRITE (write memory)
IREAD (indexed read)
IWRITE (indexed write)
READSP (read stack pointer)
RUN (run user program)
also lists external frequencies required to achieve a standard baud rate of 9600 bps. The
Wait one bit time after each echo before sending the next byte.
ECHO
Notes:
4
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
FROM HOST
READ
0
1
1
READ
2
TST
for this limit.
MISSING STOP BIT
3
4
) upon entry into monitor mode. If monitor mode was entered with V
ADDRESS
Figure 19-14. Break Transaction
4
Figure 19-15. Read Transaction
MC68HC908GR16 Data Sheet, Rev. 5.0
HIGH
5
1
6
ADDRESS
HIGH
7
3 = Cancel command delay, 11 bit times
4 = Wait 1 bit time before sending next byte.
NOTE
4
ADDRESS
LOW
1
2-STOP BIT DELAY BEFORE ZERO ECHO
ADDRESS
LOW
0
1
2
3, 2
3
4
20.7 5.0-Volt Control Timing
DATA
5
6
RETURN
4
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