mc68hc908gp32 Freescale Semiconductor, Inc, mc68hc908gp32 Datasheet - Page 139
mc68hc908gp32
Manufacturer Part Number
mc68hc908gp32
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC908GP32.pdf
(266 pages)
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13.4.3.3 Data Sampling
The receiver samples the PTE1/RxD pin at the RT clock rate. The RT clock is an internal signal with a
frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at
the following times (see
To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three
logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Table 13-2
Start bit verification is not successful if any two of the three verification samples are logic 1s. If start bit
verification is not successful, the RT clock is reset and a new search for a start bit begins.
Freescale Semiconductor
•
•
RT CLOCK
RT CLOCK
SAMPLES
PTE1/RxD
After every start bit
After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit
samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
CLOCK
RESET
STATE
RT
summarizes the results of the start bit verification samples.
Figure
RT3, RT5, and RT7
QUALIFICATION
13-6):
Samples
START BIT
Figure 13-6. Receiver Data Sampling
000
001
010
011
100
101
110
111
Table 13-2. Start Bit Verification
MC68HC908GP32 Data Sheet, Rev. 10
VERIFICATION
START BIT
Verification
Start Bit
Yes
Yes
Yes
Yes
No
No
No
No
START BIT
SAMPLING
DATA
Noise Flag
0
1
1
0
1
0
0
0
Functional Description
LSB
139
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