mc68hc908gp20 Freescale Semiconductor, Inc, mc68hc908gp20 Datasheet - Page 108

• Manufacturer Part Number: mc68hc908gp20
• Description: M68hc08 Family Of 8-bit Microcontroller Units Mcus
• Manufacturer: Freescale Semiconductor, Inc

7.2 Introduction
Advance Information
108
7.6.5
7.6.6
7.7
7.8
7.8.1
7.8.2
7.8.3
7.9
7.9.1
7.9.2
7.9.3
This section describes the clock generator module. The CGMC
generates the crystal clock signal, CGMXCLK, which operates at the
frequency of the crystal. The CGMC also generates the base clock
signal, CGMOUT, which is based on either the crystal clock divided by
two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two. In
user mode, CGMOUT is the clock from which the SIM derives the
system clocks, including the bus clock, which is at a frequency of
CGMOUT/2. In monitor mode, PTC3 determines the bus clock. The PLL
is a fully functional frequency generator designed for use with crystals or
ceramic resonators. The PLL can generate an 8-MHz bus frequency
using a 32-kHz crystal.
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 135
PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . . 131
PLL Reference Divider Select Register. . . . . . . . . . . . . . . 132
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
CGMC During Break Interrupts . . . . . . . . . . . . . . . . . . . . . 134
Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . 135
Parametric Influences on Reaction Time . . . . . . . . . . . . . 136
Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
MC68HC908GP20
Freescale Semiconductor
—
Rev 2.1