mc68hc908jw32 Freescale Semiconductor, Inc, mc68hc908jw32 Datasheet - Page 200

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mc68hc908jw32

Manufacturer Part Number
mc68hc908jw32
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Low-Voltage Inhibit (LVI)
17.3.1 Low V
The low V
below the trip voltage, V
CONFIG1 register.
17.3.2 Polled LVI Operation
In applications that can operate at V
the LVIOUT bit. In the CONFIG1 register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
17.3.3 Forced Reset Operation
In applications that require V
module to reset the MCU when V
and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets.
17.3.4 Voltage Hysteresis Protection
Once the LVI has triggered (by having V
V
continually entering and exiting reset if V
V
200
DD
TRIPF1
rises above the rising trip point voltage, V
by the hysteresis voltage, V
DD
DETECTOR
detector circuit monitors the V
LOW V
DD
V
DD
Detector
DD
TRIPF1
V
V
FROM CONFIG1
DD
DD
DD
> V
≤ V
LVIPWRD
. The V
Figure 17-2. LVI Module Block Diagram
TRIPR1
TRIPF1
to remain above the V
DD
DD
falls below the V
MC68HC908JW32 Data Sheet, Rev. 5
HYS
= 1
= 0
DD
levels below the V
DD
.
DD
LVI circuit can be disabled by the setting the LVIPWRD bit in
fall below V
DD
is approximately equal to V
TRIPR1
voltage and forces a LVI reset when the V
STOP INSTRUCTION
TRIPF1
. This prevents a condition in which the MCU is
TRIPF1
TRIPF1
TRIPF1
level. In the CONFIG1 register, the LVIPWRD
), the LVI will maintain a reset condition until
TO LVISR
level, enabling LVI resets allows the LVI
FROM CONFIG1
LVIOUT
level, software can monitor V
LVIRSTD
FROM CONFIG1
LVISTOP
TRIPF1
. V
TRIPR1
LVI RESET
Freescale Semiconductor
is greater than
DD
DD
voltage falls
by polling

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