mc68hc908ap8a Freescale Semiconductor, Inc, mc68hc908ap8a Datasheet - Page 82

• Manufacturer Part Number: mc68hc908ap8a
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Clock Generator Module (CGM)
The operating range of the VCO is programmable for a wide range of frequencies and for maximum
immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f
CGMXFC pin changes the frequency within this range. By design, f
center-of-range frequency, f
(L × 2
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency,
f
factor, R. The divider’s output is the final reference clock, CGMRDV, running at a frequency,
f
(1MHz–8MHz), always set R = 1 for specified performance. With an external high-frequency clock
source, use R to divide the external frequency to between 1MHz and 8MHz.
The VCO’s output clock, CGMVCLK, running at a frequency, f
pre-scaler divider and a programmable modulo divider. The pre-scaler divides the VCO clock by a
power-of-two factor P (the CGMPCLK) and the modulo divider reduces the VCO clock by a factor, N. The
dividers’ output is the VCO feedback clock, CGMVDV, running at a frequency, f
6.3.6 Programming the PLL
The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock,
CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The
loop filter then slightly alters the DC voltage on the external capacitor connected to CGMXFC based on
the width and direction of the correction pulse. The filter can make fast or slow corrections depending on
its mode, described in
reference frequency determines the speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final
reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final
reference frequency, f
this comparison.
6.3.4 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two operating modes:
82
RCLK
RDV
•
•
•
•
•
= f
, and is fed to the PLL through a programmable modulo reference divider, which divides f
E
Phase detector
Loop filter
Lock detector
Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the
VCO. This mode is used at PLL start up or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in
the PLL bandwidth control register. (See
Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the
VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL
enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected
as the base clock source. (See
tracking mode when not in acquisition mode or when the ACQ bit is set.
)f
RCLK
NOM
.
/R. With an external crystal
RDV
6.3.4 Acquisition and Tracking
. The circuit determines the mode of the PLL and the lock condition based on
NOM
for more information.)
, (125 kHz) times a linear factor, L, and a power-of-two factor, E, or
MC68HC908AP A-Family Data Sheet, Rev. 3
6.3.8 Base Clock Selector
6.5.2 PLL Bandwidth Control
Modes. The value of the external capacitor and the
VCLK
VRS
Circuit.) The PLL is automatically in
. Modulating the voltage on the
, is fed back through a programmable
VRS
is equal to the nominal
VDV
Register.)
= f
Freescale Semiconductor
VCLK
/(N × 2
RCLK
P
). (See
by a