mc68hc908ap8cfa Freescale Semiconductor, Inc, mc68hc908ap8cfa Datasheet - Page 206

• Manufacturer Part Number: mc68hc908ap8cfa
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Infrared Serial Communications Interface Module (IRSCI)
RPF — Reception in Progress Flag Bit
12.9.6 IRSCI Data Register
The IRSCI data register is the buffer between the internal data bus and the receive and transmit shift
registers. Reset has no effect on data in the IRSCI data register.
R7/T7–R0/T0 — Receive/Transmit Data Bits
12.9.7 IRSCI Baud Rate Register
The baud rate register selects the baud rate for both the receiver and the transmitter.
CKS — Baud Clock Input Select
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
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This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit
search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start
bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. Polling
RPF before disabling the SCI module or entering stop mode can show whether a reception is in
progress.
Reading the IRSCDR accesses the read-only received data bits, R7–R0. Writing to the IRSCDR writes
the data to be transmitted, T7–T0. Reset has no effect on the IRSCDR.
This read/write bit selects the source clock for the baud rate generator. Reset clears the CKS bit,
selecting CGMXCLK.
These read/write bits select the baud rate prescaler divisor as shown in
and SCP0.
1 = Reception in progress
0 = No reception in progress
1 = Bus clock drives the baud rate generator
0 = CGMXCLK drives the baud rate generator
Address:
Address:
Do not use read/modify/write instructions on the IRSCI data register.
Reset:
Reset:
Read:
Read:
Write:
Write:
$0045
$0046
CKS
Bit 7
Bit 7
R7
T7
0
Figure 12-19. IRSCI Baud Rate Register (IRSCBR)
Figure 12-18. IRSCI Data Register (IRSCDR)
= Unimplemented
R6
T6
6
6
0
0
MC68HC908AP Family Data Sheet, Rev. 4
SCP1
R5
T5
5
5
0
NOTE
Unaffected by reset
SCP0
R4
T4
4
4
0
R3
T3
R
R
3
3
0
= Reserved
SCR2
R2
T2
2
2
0
Table
SCR1
R1
T1
1
1
0
12-7. Reset clears SCP1
Freescale Semiconductor
SCR0
Bit 0
Bit 0
R0
T0
0