mc68hc908mr32 Freescale Semiconductor, Inc, mc68hc908mr32 Datasheet - Page 182

• Manufacturer Part Number: mc68hc908mr32
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

System Integration Module (SIM)
14.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in
can come from either an external oscillator or from the on-chip phase-locked loop (PLL) circuit. See
Chapter 4 Clock Generator Module
14.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four
or the PLL output (CGMVCLK) divided by four. See
14.2.2 Clock Startup from POR or LVI Reset
When the power-on reset (POR) module or the low-voltage inhibit (LVI) module generates a reset, the
clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096
CGMXCLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire
period. The internal bus (IBUS) clocks start upon completion of the timeout.
182
PIN LOGIC
RESET
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
SIM RESET STATUS REGISTER
RESET PIN CONTROL
POR CONTROL
CONTROL
CONTROL
AND PRIORITY DECODE
INTERRUPT CONTROL
CLOCK
Figure 14-1. SIM Block Diagram
WAIT
(CGM).
CLOCK GENERATORS
RESET
COUNTER
Chapter 4 Clock Generator Module
SIM
÷ 2
CONTROL
MASTER
RESET
MODULE WAIT
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
CPU INTERFACE
INTERRUPT SOURCES
Figure
Freescale Semiconductor
14-2. This clock
(CGM).