mc68hc908mr32 Freescale Semiconductor, Inc, mc68hc908mr32 Datasheet - Page 187

• Manufacturer Part Number: mc68hc908mr32
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

14.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
14.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the return-from-interrupt
(RTI) instruction recovers the CPU register contents from the stack so that normal processing can
resume.
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared). See
Freescale Semiconductor
1. Interrupts:
2. Reset
3. Break interrupts
INTERRUPT
MODULE
I BIT
R/W
IDB
IAB
a. Maskable hardware CPU interrupts
b. Non-maskable software interrupt instruction (SWI)
Figure 14-7
DUMMY
shows interrupt entry timing.
DUMMY
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
SP
PC – 1[7:0] PC – 1[15:8]
SP – 1
Figure 14-7
SP – 2
Figure
X
.
Figure 14-9
Interrupt Entry
SP – 3
14-8.
A
SP – 4
shows interrupt recovery timing.
CCR
VECT H
V DATA H
VECT L
V DATA L
START
ADDR
OPCODE
Exception Control
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