mc68hc908mr8 Freescale Semiconductor, Inc, mc68hc908mr8 Datasheet - Page 131

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mc68hc908mr8

Manufacturer Part Number
mc68hc908mr8
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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8.6.3 PLL Programming Register
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
NOTE:
The PLL programming register (PPG) contains the programming
information for the modulo feedback divider and the programming
information for the hardware configuration of the VCO.
MUL[7:4] — Multiplier Select Bits
The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
Reset:
dress:
Read:
Write:
Ad-
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. See
8.4.2.4 Programming the
bits configures the modulo feedback divider the same as a value of
$1. Reset initializes these bits to $6 to give a default multiply value
of 6.
$005E
MUL7
MUL7:MUL6:MUL5:MUL4
Bit 7
0
Figure 8-7. PLL Programming Register (PPG)
Clock Generator Module (CGM)
Table 8-1. VCO Frequency Multiplier (N) Selection
MUL6
0000
0001
0010
0011
1101
1110
1111
6
1
MUL5
5
1
PLL. A value of $0 in the multiplier select
MUL4
4
0
VCO Frequency Multiplier (N)
VRS7
8.4.2.1 PLL Circuits
3
0
Clock Generator Module (CGM)
VRS6
2
1
13
14
15
1
1
2
3
VRS5
CGM Registers
1
1
Technical Data
and
VRS4
Bit 0
0
131

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