mc68hc908mr8 Freescale Semiconductor, Inc, mc68hc908mr8 Datasheet - Page 330
mc68hc908mr8
Manufacturer Part Number
mc68hc908mr8
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC908MR8.pdf
(372 pages)
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Break (BRK)
20.3 Features
20.4 Functional Description
20.4.1 Flag Protection During Break Interrupts
Technical Data
330
Features of the break module include:
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal to the
CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU
instruction. The program counter vectors to $FFFC and $FFFD ($FEFC
and $FEFD in monitor mode).
These events can cause a break interrupt to occur:
When a CPU-generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the microcontroller unit
(MCU) to normal operation.
module.
The BCFE bit in the system integration module (SIM) break flag control
register (SBFCR) enables software to clear status bits during the break
state.
•
•
•
•
•
•
Accessible input/output (I/O) registers during the break interrupt
Central processor unit (CPU) generated break interrupts
Software-generated break interrupts
Computer operating properly (COP) disabling during break
interrupts
A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
Software writes a logic 1 to the BRKA bit in the break status and
control register.
Break (BRK)
Figure 20-1
shows the structure of the break
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
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