mc68hc908rc24d Freescale Semiconductor, Inc, mc68hc908rc24d Datasheet - Page 147

• Manufacturer Part Number: mc68hc908rc24d
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

13.7 TIM0I During Break Interrupts
13.8 I/O Registers
13.8.1 TIM0I Status and Control Register
MC68HC908RC24 — Rev. 1.1
Freescale Semiconductor
A break interrupt stops the TIM0I counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the break flag control register (BFCR) enables software to clear status
bits during the break state. (See
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
These I/O registers control and monitor operation of the TIM0I:
The TIM0I status and control register:
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TIM0I status and control register (TSC)
TIM0I counter registers (TCNTH and TCNTL)
TIM0I counter modulo registers (TMODH and TMODL)
Enables TIM0I overflow interrupt
Flags TIM0I overflows
Stops the TIM0I counter
Resets the TIM0I counter
Prescales the TIM0I counter clock
Modulo Timer (TIM0I)
Section 18. Break Module
TIM0I During Break Interrupts
Modulo Timer (TIM0I)
Advance Information
(BRK).)
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