mc68hc908rc24d Freescale Semiconductor, Inc, mc68hc908rc24d Datasheet - Page 58

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mc68hc908rc24d

Manufacturer Part Number
mc68hc908rc24d
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Central Processor Unit (CPU)
5.6.1 Wait Mode
5.6.2 Stop Mode
5.7 CPU During Break Interrupts
5.8 Instruction Set Summary
Advance Information
58
The WAIT instruction:
The STOP instruction:
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
If the break module is enabled, a break interrupt causes the CPU to
execute the software interrupt instruction (SWI) at the completion of the
current CPU instruction. (See
program counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor
mode).
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
Table 5-1
Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
provides a summary of the M68HC08 instruction set.
Central Processor Unit (CPU)
Section 7. Break Module
MC68HC908RC24 — Rev. 1.1
Freescale Semiconductor
(BRK).) The

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