mc68hc05p1a Freescale Semiconductor, Inc, mc68hc05p1a Datasheet - Page 60

• Manufacturer Part Number: mc68hc05p1a
• Description: General Release Specification
• Manufacturer: Freescale Semiconductor, Inc

Input/Output Ports
7.7 I/O Port Programming
General Release Specification
Each pin on ports A through D (except pin 7 of port D) may be
programmed as an input or an output under software control as shown
in
is determined by the state of its corresponding bit in the associated port
data direction register (DDR). A pin is configured as an output if its
corresponding DDR bit is set to a logic 1. A pin is configured as an input
if its corresponding DDR bit is cleared to a logic 0.
*Does not affect input, but stored to data register
**If enabled via mask option
DDRA
Table
*Does not affect input, but stored to data register
*Does not affect input, but stored to data register
Freescale Semiconductor, Inc.
0
1
DDRB
DDRC
For More Information On This Product,
0
1
0
1
7-1,
Input, Hi-Z
I/O Pin
Output
Mode
Go to: www.freescale.com
Table
Input, Hi-Z
Input, Hi-Z
I/O Pin
I/O Pin
Output
Output
Mode
Mode
Input/Output Ports
Table 7-1. Port A I/O Pin Functions
Table 7-2. Port B I/O Pin Functions
Table 7-3. Port C I/O Pin Functions
7-2,
DDRA0–DDRA7
DDRA0–DDRA7
DDRA @ $0004
Accesses to
Table
Read/Write
DDRB5–DDRB7
DDRB0–DDRB7
DDRC0–DDRA7
DDRC0–DDRA7
DDRB @ $0005
DDRC @ $0006
Accesses to
Accesses to
Read/Write
Read/Write
7-3, and
Table
PA0–PA7
I/O Pin
Accesses to Data
Register @ $0000
Read
7-4. The direction of a pin
PC0–PC7
PB5–PB7
I/O Pin
I/O Pin
MC68HC05P1A
Read
Read
Register @ $0001
Register @ $0002
Accesses to Data
Accesses to Data
PA0–PA7
Write
*
PC0–PC7
PB5–PB7
Write
Write
Enabled**
Disabled
Source
—
*
*
IRQ
Rev. 3.0