mc68hc05p1a Freescale Semiconductor, Inc, mc68hc05p1a Datasheet - Page 61

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mc68hc05p1a

Manufacturer Part Number
mc68hc05p1a
Description
General Release Specification
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MC68HC05P1A
NOTE:
Rev. 3.0
To avoid generating a glitch on an I/O port pin, data should be written to
the I/O port data register before writing a logical 1 to the corresponding
data direction register.
At power-on or reset, all DDRs are cleared, which configures all port pins
as inputs. The DDRs are capable of being written to or read by the
processor. During the programmed output state, a read of the data
register will actually read the value of the output data latch and not the
level on the I/O port pin.
*Does not affect input, but stored to data register, PD7 is input-only
Freescale Semiconductor, Inc.
DDRD
For More Information On This Product,
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Input, Hi-Z
I/O Pin
Output
Mode
Input/Output Ports
Table 7-4. Port D I/O Pin Functions
DDRD @ $0007
Accesses to
Read/Write
DDRD5
DDRD5
General Release Specification
I/O Pin
Read
PD5
Accesses to Data
Register @ $0003
I/O Port Programming
Input/Output Ports
Write
PD5
*

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