mc68hc05p1a Freescale Semiconductor, Inc, mc68hc05p1a Datasheet - Page 70

• Manufacturer Part Number: mc68hc05p1a
• Description: General Release Specification
• Manufacturer: Freescale Semiconductor, Inc

16-Bit Timer
General Release Specification
NOTES:
AND OUTPUT PIN
COMPARE FLAG
16-BIT FREE-
COUNTER
1.
2.
3.
RUNNING
OUTPUT
REGISTER
REGISTER
COMPARE
COMPARE
CLOCK
LATCH
PH2
The CPU write to the compare register may take place at any time, but a compare only occurs at timer state T01. Thus, up
Internal compare takes place during timer state T01.
The output compare flag bit (OCF) is set at timer state T11 which follows the comparison match ($FFED in this example).
to a four cycle difference may exist between the write to the compare register and the actual compare.
Figure 8-7. Output Compare Software Initialization Example
$FFEB
Figure 8-8. State Timing Diagram for Output Compare
9B
B6
BE
B7
B6
BF
9A
.
.
.
.
XX
XX
16
13
17
.
.
.
.
Freescale Semiconductor, Inc.
CPU WRITES $FFED
For More Information On This Product,
$FFEC
SEI
LDA
LDX
STA
LDA
STX
CLI
.
.
.
.
Go to: www.freescale.com
DATAH
DATAL
OCRH
TSR
OCRL
.
.
.
.
16-Bit Timer
(NOTE 1)
(NOTE 2)
$FFED
BLOCK INTERRUPTS
HI BYTE FOR COMPARE
LO BYTE FOR COMPARE
INHIBIT OUTPUT COMPARE
ARM OCF BIT TO CLEAR
READY FOR NEXT COM-
PARE
.
.
.
.
$FFEE
$FFED
MC68HC05P1A
(NOTE 3)
$FFEF
—
Rev. 3.0