mc68hc05pv8 Freescale Semiconductor, Inc, mc68hc05pv8 Datasheet - Page 142

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mc68hc05pv8

Manufacturer Part Number
mc68hc05pv8
Description
Hcmos Microcontroller Unit
Manufacturer
Freescale Semiconductor, Inc
Datasheet
T echnical Data
10.6.2 A/D Data Register
10.7 A/D During WAIT Mode
Technical Data
NOTE:
Channel 0 and 7–15 convert internal signals which cannot be accessed
externally.
One 8-bit result register is provided. This register is updated each time
COCO is set.
The A/D converter continues normal operation during WAIT mode. To
decrease power consumption during WAIT it is recommended that both
the ADON and ADRC bits in the A/D status and control registers be
cleared if the A/D converter is not being used. If the A/D converter is in
use and the system clock rate is above 1.0 MHz it is recommended that
the ADRC bit be cleared.
As the A/D converter continues to function normally in WAIT mode the
COCO bit is not cleared.
$000E
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
CH3
1
1
1
1
1
Bit 7
bit 7
U
Analog to Digital Converter
Go to: www.freescale.com
Figure 10-3 A/D Data Register (ADDR)
CH2
Table 10-1 A/D Channel Assignments
0
0
0
0
1
bit 6
U
6
CH1
bit 5
X
0
0
1
1
U
5
bit 4
CH0
U
4
X
0
1
0
1
bit 3
Channel
U
3
12-15
MC68HC(8)05PV8/A — Rev. 1.9
10
11
8
9
bit 2
U
2
(V
REFH
Signal
V
V
V
V
bit 1
U
REFH
1
REFL
REFL
REFL
+V
REFL
)/2
Bit 0
bit 0
U

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