mc68hc11e0fnr2 Freescale Semiconductor, Inc, mc68hc11e0fnr2 Datasheet - Page 110

• Manufacturer Part Number: mc68hc11e0fnr2
• Description: Hc11 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Communications Interface (SCI)
7.7.1 Serial Communications Data Register
SCDR is a parallel register that performs two functions:
Reads access the receive data buffer and writes access the transmit data buffer. Receive and transmit
are double buffered.
7.7.2 Serial Communications Control Register 1
The SCCR1 register provides the control bits that determine word length and select the method used for
the wakeup feature.
R8 — Receive Data Bit 8
T8 — Transmit Data Bit 8
Bit 5 — Unimplemented
M — Mode Bit (select character format)
WAKE — Wakeup by Address Mark/Idle Bit
Bits [2:0] — Unimplemented
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If M bit is set, R8 stores the ninth bit in the receive data character.
If M bit is set, T8 stores the ninth bit in the transmit data character.
Always reads 0
Always read 0
0 = Start bit, 8 data bits, 1 stop bit
1 = Start bit, 9 data bits, 1 stop bit
0 = Wakeup by IDLE line recognition
1 = Wakeup by address mark (most significant data bit set)
The receive data register when it is read
The transmit data register when it is written
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 7-4. Serial Communications Control Register 1 (SCCR1)
Figure 7-3. Serial Communications Data Register (SCDR)
I = Indeterminate after reset
$102C
$102F
R7/T7
Bit 7
Bit 7
R8
I
= Unimplemented
R6/T6
T8
6
6
I
M68HC11E Family Data Sheet, Rev. 5.1
R5/T5
5
5
0
Indeterminate after reset
R4/T4
M
4
4
0
WAKE
R3/T3
3
3
0
R2/T2
2
2
0
R1/T1
1
1
0
Freescale Semiconductor
R0/T0
Bit 0
Bit 0
0