mc68hc11e0fnr2 Freescale Semiconductor, Inc, mc68hc11e0fnr2 Datasheet - Page 171

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mc68hc11e0fnr2

Manufacturer Part Number
mc68hc11e0fnr2
Description
Hc11 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
10.17 Serial Peripheral Interface Timing Characteristics
Freescale Semiconductor
1. V
2. Time to data active from high-impedance state
3. Assumes 200 pF load on SCK, MOSI, and MISO pins
Num
10
11
wise noted
1
2
3
4
5
6
7
8
9
DD
= 5.0 Vdc ±10%, V
Frequency of operation
E-clock period
Operating frequency
Cycle time
Enable lead time
Enable lag time
Clock (SCK) high time
Clock (SCK) low time
Data setup time (inputs)
Data hold time (inputs)
Slave access time
Disable time (hold time
Data valid
Data hold time (outputs)
E clock
Master
Slave
Master
Slave
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
CPHA = 0
CPHA = 1
to high-impedance state)
Slave
(after enable edge)
Characteristic
(3)
(after enable edge)
(2)
SS
(2)
= 0 Vdc, T
(1)
A
= T
M68HC11E Family Data Sheet, Rev. 5.1
L
to T
t
t
t
t
w(SCKH)m
Symbol
w(SCKL)m
w(SCKH)s
w(SCKL)s
t
H
t
t
CYC(m)
f
CYC(s)
t
t
lead(s)
f
t
t
t
, all timing is shown with respect to 20% V
op(m)
su(m)
lag(s)
t
op(s)
su(s)
CYC
h(m)
t
h(s)
t
f
t
dis
t
ho
o
a
v
t
t
t
t
CYC
CYC
CYC
CYC
f
Min
333
o
1/2
1/2
30
30
30
30
dc
dc
/32
2
1
1
1
0
0
0
–25
–25
–25
–25
Serial Peripheral Interface Timing Characteristics
E9
16 t
16 t
Max
f
3.0
32
40
40
50
50
o
f
o
/2
CYC
CYC
t
t
t
t
CYC
CYC
CYC
CYC
f
o
DD
Min
333
1/2
1/2
/128
dc
dc
30
30
30
30
2
1
1
1
0
0
0
–25
–25
–25
–25
and 70% V
E20
64 t
64 t
Max
DD
128
f
3.0
o
40
40
50
50
f
/2
o
CYC
CYC
, unless other-
MHz
Unit
MHz
t
t
t
CYC
CYC
CYC
ns
ns
ns
ns
ns
ns
ns
ns
ns
171

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