mc68hc11f1cpu5 Freescale Semiconductor, Inc, mc68hc11f1cpu5 Datasheet - Page 22

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mc68hc11f1cpu5

Manufacturer Part Number
mc68hc11f1cpu5
Description
8-bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
INIT — RAM and I/O Mapping (MC68HC11F1 only)
RAM[3:0] — Internal RAM Map Position
REG[3:0] — 96-Byte Register Block Map Position
GWOM — Port G Wired-OR Mode Option
22
OPT2 — System Configuration Option Register 2
MOTOROLA
RESET
RESET:
The INIT register can be written only once in first 64 cycles out of reset in normal modes, or at any time
in special modes.
These bits determine the upper four bits of the RAM address and allow mapping of the RAM to any four-
Kbyte boundary. Refer to Table 10.
These bits determine bits the upper 4 bits of the register block and allow mapping of the register block
to any four-Kbyte boundary. Refer to Table 10.
Refer to 7.8 Parallel I/O Registers, page 36.
GWOM
RAM3
Bit 7
Bit 7
0
0
The register diagram above applies to the MC68HC11F1 only. A diagram and bit
descriptions of the INIT register in the MC68HC11FC0 are provided elsewhere in
this section.
RAM[3:0]
CWOM
RAM2
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
6
0
6
0
Table 10 RAM and Register Mapping
CLK4X
RAM1
$A000-$A3FF
$B000-$B3FF
$C000-$C3FF
$D000-$D3FF
$E000-$E3FF
$F000-$F3FF
$0000-$03FF
$1000-$13FF
$2000-$23FF
$3000-$33FF
$4000-$43FF
$5000-$53FF
$6000-$63FF
$7000-$73FF
$8000-$83FF
$9000-$93FF
5
1
5
0
Location
LIRDV
RAM0
4
0
4
0
NOTE
REG3
3
0
3
0
REG[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SPRBYP
REG4
2
0
2
0
$C000-$C05F
$D000-$D05F
$A000-$A05F
$B000-$B05F
$E000-$E05F
$F000-$F05F
$0000-$005F
$1000-$105F
$2000-$205F
$3000-$305F
$4000-$405F
$5000-$505F
$6000-$605F
$7000-$705F
$8000-$805F
$9000-$905F
Location
REG1
1
0
1
0
MC68HC11F1/FC0
REG0
Bit 0
MC68HC11FTS/D
Bit 0
0
1
$x03D
$x038

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