mc68hc11f1cpu5 Freescale Semiconductor, Inc, mc68hc11f1cpu5 Datasheet - Page 26

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mc68hc11f1cpu5

Manufacturer Part Number
mc68hc11f1cpu5
Description
8-bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
5.2 Reset and Interrupt Registers
OPTION — System Configuration Options
Bits [7:6], [4:2]
IRQE — IRQ Select Edge Sensitive Only
26
RESET:
MOTOROLA
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes.
Refer to 4.3 System Initialization Registers, page 23, and 11.3 A/D Registers, page 56.
Vector Address
0 = Low level recognition
1 = Falling edge recognition
FFDC, DD
FFDA, DB
FFDE, DF
FFEA, EB
FFEC, ED
FFFC, FD
FFC0, C1
FFD4, D5
FFD6, D7
FFD8, D9
FFEE, EF
FFFA, FB
FFE0, E1
FFE2, E3
FFE4, E5
FFE6, E7
FFE8, E9
FFFE, FF
FFF0, F1
FFF2, F3
FFF4, F5
FFF6, F7
FFF8, F9
to
ADPU
Bit 7
0
CSEL
SCI Serial System
SPI Serial Transfer Complete
Pulse Accumulator Input Edge
Pulse Accumulator Overflow
Timer Overflow
Timer Input Capture 4/Output Compare 5
Timer Output Compare 4
Timer Output Compare 3
Timer Output Compare 2
Timer Output Compare 1
Timer Input Capture 3
Timer Input Capture 2
Timer Input Capture 1
Real-Time Interrupt
IRQ
XIRQ Pin
Software Interrupt
Illegal Opcode Trap
COP Failure
Clock Monitor Fail
RESET
6
0
Table 11 Interrupt and Reset Vector Assignments
SCI Transmit Complete
SCI Transmit Data Register Empty
SCI Idle Line Detect
SCI Receiver Overrun
SCI Receive Data Register Full
IRQE*
Interrupt Source
5
0
Reserved
DLY*
4
1
CME
3
0
FCME*
CCR Mask
2
0
None
None
None
None
None
X Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
CR1*
Local Mask
1
0
NOCOP
PAOVI
I4/O5I
None
None
TCIE
SPIE
OC4I
OC3I
OC2I
OC1I
None
None
None
CME
PAII
RTII
ILIE
IC3I
IC2I
IC1I
RIE
RIE
TOI
TIE
MC68HC11F1/FC0
CR0*
MC68HC11FTS/D
Bit 0
0
Flag Bit
PAOVF
I4/O5F
TDRE
RDRF
OC4F
OC3F
OC2F
OC1F
None
None
None
None
None
None
None
IDLE
SPIF
PAIF
IC3F
IC2F
IC1F
RTIF
TOF
OR
TC
$x039

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