mc68hc705p6a Freescale Semiconductor, Inc, mc68hc705p6a Datasheet - Page 38

• Manufacturer Part Number: mc68hc705p6a
• Description: M68hc05 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Input/Output Ports
6.3 Port B
Port B is a 3-bit bidirectional port which can share pins PB5–PB7 with the SIOP communications
subsystem. The port B data register is located at address $0001 and its data direction register (DDR) is
located at address $0005. The contents of the port B data register are indeterminate at initial powerup
and must be initialized by user software. Reset does not affect the data registers, but clears the DDRs,
thereby setting all of the port pins to input mode. Writing a 1 to a DDR bit sets the corresponding port pin
to output mode (see
Port B may be used for general I/O applications when the SIOP subsystem is disabled. The SPE bit in
register SPCR is used to enable/disable the SIOP subsystem. When the SIOP subsystem is enabled, port
B registers are still accessible to software. Writing to either of the port B registers while a data transfer is
under way could corrupt the data. See
SIOP subsystem.
6.4 Port C
Port C is an 8-bit bidirectional port which can share pins PC3–PC7 with the A/D subsystem. The port C
data register is located at address $0002 and its data direction register (DDR) is located at address
$0006. The contents of the port C data register are indeterminate at initial powerup and must be initialized
by user software. Reset does not affect the data registers, but clears the DDRs, thereby setting all of the
port pins to input mode. Writing a 1 to a DDR bit sets the corresponding port pin to output mode (see
Figure
Port C may be used for general I/O applications when the A/D subsystem is disabled. The ADON bit in
register ADSC is used to enable/disable the A/D subsystem. Care must be exercised when using pins
PC0–PC2 while the A/D subsystem is enabled. Accidental changes to bits that affect pins PC3–PC7 in
the data or DDR registers will produce unpredictable results in the A/D subsystem. See
Subsystem.
38
INTERNAL HC05
DATA BUS
6-3).
WRITE $0005
WRITE $0001
READ $0005
READ $0001
Figure
RESET
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
(RST)
6-2).
Figure 6-2. Port B I/O Circuitry
DATA DIRECTION
REGISTER BIT
REGISTER BIT
Chapter 7 Serial Input/Output Port (SIOP)
DATA
OUTPUT
for a discussion of the
Freescale Semiconductor
Chapter 9 Analog
PIN
I/O