mpc8536e Freescale Semiconductor, Inc, mpc8536e Datasheet

mpc8536e

Manufacturer Part Number

mpc8536e

Description

Mpc8536e Powerquicctm Iii Integrated Processor Hardware Specifications

Manufacturer

Freescale Semiconductor, Inc

Datasheet

1.MPC8536E.pdf (128 pages)

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MPC8536E

PowerQUICC™ III

Integrated Processor

Hardware Specifications

• High-performance, 32-bit e500 core, scaling up to

• Integrated L1/L2 cache

• DDR2/DDR3 SDRAM memory controller with full ECC

• Integrated security engine (SEC) optimized to process all

• Enhanced Serial peripheral interfaces (eSPI)

• Two enhanced three-speed Ethernet controllers (eTSECs)

This document contains information on a product under development. Freescale reserves the

right to change or discontinue this product without notice.

1.5 GHz, that implements the Power Architecture™

technology

– 36-bit physical addressing

– Double-precision embedded floating point APU using

– Embedded vector and scalar single-precision

– Memory management unit (MMU)

– L1 cache—32-Kbyte data and 32-Kbyte instruction

– L2 cache—512-Kbyte (8-way set associative)

support

– One 64-bit/32-bit data bus

– Up to 333-MHz clock (667-MHz data rate)

– Supporting up to 16 Gbytes of main memory

– Using ECC, detects and corrects all single-bit errors and

– Invoke a level of system power management by

– Both hardware and software options to support

the algorithms associated with IPsec, IKE, SSL/TLS,

iSCSI, SRTP, IEEE Std 802.16e™, and 3GPP.

– XOR engine for parity checking in RAID storage

– Support boot capability from eSPI

with SGMII support

– Three-speed support (10/100/1000 Mbps)

– Two IEEE Std 802.3™, IEEE 802.3u, IEEE 802.3x,

64-bit operands

floating-point APUs using 32- or 64-bit operands

detects all double-bit errors and all errors within a nibble

asserting MCKE SDRAM signal on-the-fly to put the

memory into a low-power sleep mode

battery-backed main memory

applications

IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab, and

IEEE Std 1588™-compatible controllers

• High-speed interfaces (multiplexed) supporting:

• PCI 2.2 compatible PCI controller

• Three universal serial bus (USB) dual-role controllers

• 133-MHz, 32-bit, enhanced local bus (eLBC) with memory

• Enhanced secured digital host controller (eSDHC) used for

• Integrated four-channel DMA controller

• Dual I

• Programmable interrupt controller (PIC)

• Power management, low standby power

• System performance monitor

• IEEE Std 1149.1™-compatible, JTAG boundary scan

• 783-pin FC-PBGA package, 29 mm × 29 mm

– Support for various Ethernet physical interfaces: GMII,

– Support TCP/IP acceleration and QOS features

– MAC address recognition and RMON statistics support

– Support ARP parsing and generating wake-up events

– Support accepting and storing packets while in deep

– Three PCI Express interfaces

– Two SGMII interfaces

– Two Serial ATA (SATA) Controllers support SATA I and

comply with USB specification revision 2.0

controller

SD/MMC card interface

– Support boot capability from eSDHC

receiver/transmitter (DUART) support

– Support Doze, Nap, Sleep, Jog, and Deep Sleep mode

– PMC wake on: LAN activity, USB connection or remote

TBI, RTBI, RGMII, MII, RGMII, RMII, and SGMII

based on the parsing results while in deep sleep mode

sleep mode

SATA II data rates

wakeup, GPIO, internal timer, or external interrupt event

– PCI Express 1.0a compatible

– One x8/x4/x2/x1 PCI Express interface

– Two x4/x2/x1 ports, or,

– One x4/x2/x1 port and Two x2/x1 ports

C and dual universal asynchronous

Document Number: MPC8536EEC

FC-PBGA–783

29 mm × 29 mm

Rev. 2, 09/2009

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