mpc850de Freescale Semiconductor, Inc, mpc850de Datasheet - Page 4

no-image

mpc850de

Manufacturer Part Number
mpc850de
Description
Mpc850 Rev. A/b/c Communications Controller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mpc850deCVR50BU
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mpc850deCVR66BU
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mpc850deCZQ50BU
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mpc850deCZQ66BU
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mpc850deVR50BU
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mpc850deZQ50BU
Manufacturer:
SEMTECH
Quantity:
8 390
Part Number:
mpc850deZQ50BU
Manufacturer:
FREESCAL
Quantity:
300
Part Number:
mpc850deZQ50BU
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
mpc850deZQ80BU
Manufacturer:
FREESCAL
Quantity:
300
4
— 2-Kbyte instruction cache and 1-Kbyte data cache (Harvard architecture)
— Memory management units (MMUs) with 8-entry translation lookaside buffers (TLBs) and
— MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512 Kbytes, and
Advanced on-chip emulation debug mode
Data bus dynamic bus sizing for 8, 16, and 32-bit buses
— Supports traditional 68000 big-endian, traditional x86 little-endian and modified little-endian
— Twenty-six external address lines
Completely static design (0–80 MHz operation)
System integration unit (SIU)
— Hardware bus monitor
— Spurious interrupt monitor
— Software watchdog
— Periodic interrupt timer
— Low-power stop mode
— Clock synthesizer
— Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture
— Reset controller
— IEEE 1149.1 test access port (JTAG)
Memory controller (eight banks)
— Glueless interface to DRAM single in-line memory modules (SIMMs), synchronous DRAM
— Memory controller programmable to support most size and speed memory interfaces
— Boot chip-select available at reset (options for 8, 16, or 32-bit memory)
— Variable block sizes, 32 Kbytes to 256 Mbytes
— Selectable write protection
— On-chip bus arbiter supports one external bus master
— Special features for burst mode support
General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting
– Caches are two-way, set-associative
– Physically addressed
– Cache blocks can be updated with a 4-word line burst
– Least-recently used (LRU) replacement algorithm
– Lockable one-line granularity
fully-associative instruction and data TLBs
8 Mbytes; 16 virtual address spaces and eight protection groups
memory systems
(SDRAM), static random-access memory (SRAM), electrically programmable read-only
memory (EPROM), flash EPROM, etc.
MPC850 (Rev. A/B/C) Hardware Specifications
MOTOROLA

Related parts for mpc850de