mpc82x52a Megawin Technology, mpc82x52a Datasheet - Page 61
mpc82x52a
Manufacturer Part Number
mpc82x52a
Description
8-bit Micro-controller
Manufacturer
Megawin Technology
Datasheet
1.MPC82X52A.pdf
(72 pages)
- Current page: 61 of 72
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MEGAWIN
SFR: SCMD (ISP Sequential Command register to trigger ISP/IAP operation)
SFR: ISPCR (ISP Control register)
ISPEN: = Determine if to Enable ISP/IAP functionality
SCMD is the command port for triggering ISP activity. If SCMD is filled with sequential 46
ISPCR.7 = 1, ISP activity will be triggered.
When this register is read, the device ID of MPC82x52A will be returned (2 bytes). The MSB byte of
this device ID is F2
SWBS: = Software Boot entrance Selector
SWRST: = Software Reset trigger
CFAIL: = ISP/IAP Command Fail flag
WAIT: = Waiting time selection while the flash is busy.
Notice : Software reset actions could reset other SFR, but it never influences bits ISPEN
ISPEN
Mode Selection
Bit-7
Bit-7
0 : =
1 : =
0 : =
1 : =
0 : =
1 : =
Note: This bit will be loaded with HWBS(OR0.3) after power-up moment.
Setting this bit will cause the device reset.
0
0
1
1
and SWBS. The ISPEN and SWBS only will be reset by power-up action, while
ISPCR[2:0]
Disable ISP program to change flash.
Enable ISP program to change flash.
Boot from main-memory.
Boot from ISP memory.
The last ISP/IAP command has finished successfully.
The last ISP/IAP command fails. It could be caused since the access of flash memory
was inhibited.
0
1
0
1
SWBS
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Bit-6
Bit-6
H
and LSB byte 02
Standby
AP-memory read
AP-memory/Data-flash program
AP-memory/Data-flash page erase
SWRST
Bit-5
Bit-5
Page Erase
672384
504288
420240
252144
126072
63036
42024
21012
MPC82x52A Data Sheet
ISP-Command / Device ID
H
. IFADRL.0 is used to select HIGH/LOW byte of the device ID.
CFAIL
Bit-4
Bit-4
CPU Wait time (Oscillator cycle)
Program
1760
1320
1100
660
330
165
110
55
To Operate
Bit-3
Bit-3
-
Read
2
2
2
2
2
2
2
2
Bit-2
Bit-2
Recommended
System clock
30M~24M
24M~20M
20M~12M
12M~6M
6M~3M
3M~2M
2M~1M
< 1M
WAIT
Bit-1
Bit-1
H
, B9
Bit-0
Bit-0
H
and if
61
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