mpc8347ecvvalf Freescale Semiconductor, Inc, mpc8347ecvvalf Datasheet - Page 14

• Manufacturer Part Number: mpc8347ecvvalf
• Description: Mpc8347e Powerquicc Ii Pro Family
• Manufacturer: Freescale Semiconductor, Inc

RESET Initialization
Table 10
14
Input hold time for POR configuration signals with respect to
negation of HRESET
Time for the MPC8347E to turn off POR configuration signals
with respect to the assertion of HRESET
Time for the MPC8347E to turn on POR configuration signals
with respect to the negation of HRESET
Notes:
1. t
2. t
3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
PLL lock times
DLL lock times
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
2. The csb_clk is determined by the CLKIN and system PLL ratio. See
to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349E
PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual .
PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual .
results in the minimum and an 8:1 ratio results in the maximum.
PCI_SYNC_IN
CLKIN
is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349E
lists the PLL and DLL lock times.
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied
Parameter/Condition
Parameter/Condition
Table 9. RESET Initialization Timing Specifications (continued)
Table 10. PLL and DLL Lock Times
7680
Section 19, “Clocking.”
Min
Min
—
—
0
1
122,880
Max
Max
100
—
—
4
csb_clk cycles
t
PCI_SYNC_IN
Freescale Semiconductor
Unit
Unit
ns
ns
μs
Notes
Notes
1, 3
1, 2
3