mpc8347ecvvalf Freescale Semiconductor, Inc, mpc8347ecvvalf Datasheet - Page 19

• Manufacturer Part Number: mpc8347ecvvalf
• Description: Mpc8347e Powerquicc Ii Pro Family
• Manufacturer: Freescale Semiconductor, Inc

Figure 5
Table 15
Figure 6
Table 16
signals of the DDR controller for various loadings, which can be useful for a system utilizing the DLL.
These numbers are the result of simulations for one topology. The delay numbers will strongly depend on
the topology used. These delay numbers show the total delay for the address and command to arrive at the
DRAM devices. The actual delay could be different than the delays seen in simulation, depending on the
Freescale Semiconductor
V
V
Notes:
1. Data input threshold measurement point.
2. Data output measurement point.
OUT
TH
ADDR/CMD
MDQS[n]
provides the AC test load for the DDR bus.
shows the DDR SDRAM output timing diagram for source synchronous mode.
shows the DDR SDRAM measurement conditions.
provides approximate delay information that can be expected for the address and command
MDQ[x]
MCK[n]
MCK[n]
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Figure 6. DDR SDRAM Output Timing Diagram for Source Synchronous Mode
Output
Table 15. DDR SDRAM Measurement Conditions
Write A0
Symbol
t
DDKHAS
t
DDKHDX
Figure 5. DDR AC Test Load
t
MCK
Z
0
,t
= 50 Ω
t
DDKHCS
DDKHAX
NOOP
D0
, t
t
DDKHCX
DDKHDS
t
t
DDKHMP
DDKHMH
D1
t
DDKLDS
R
t
DDKLDX
L
= 50 Ω
MV
0.5 × GV
REF
DDR
OV
± 0.31 V
DD
DD
/2
t
DDKHME
Unit
V
V
DDR SDRAM
Notes
1
2
19