mpc8347ecvvalf Freescale Semiconductor, Inc, mpc8347ecvvalf Datasheet - Page 90

• Manufacturer Part Number: mpc8347ecvvalf
• Description: Mpc8347e Powerquicc Ii Pro Family
• Manufacturer: Freescale Semiconductor, Inc

System Design Information
21 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8347E.
21.1
The MPC8347E includes two PLLs.
21.2
Each PLL gets power through independent power supply pins (AV
level should always equal to V
low frequency filter scheme.
There are a number of ways to provide power reliably to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in
Independent filters to each PLL reduce the opportunity to cause noise injection from one PLL to the other.
The circuit filters noise in the PLL resonant frequency range from 500 kHz to 10 MHz. It should be built
with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the
recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic
(Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value
capacitor.
To minimize noise coupled from nearby circuits, each circuit should be placed as closely as possible to the
specific AV
pin, which is on the periphery of package, without the inductance of vias.
Figure 41
90
1. The platform PLL (AV
2. The e300 core PLL (AV
input. The frequency ratio between the platform and CLKIN is selected using the platform PLL
ratio configuration bits as described in
frequency ratio between the e300 core clock and the platform clock is selected using the e300
PLL ratio configuration bits as described in
System Clocking
PLL Power Supply Filtering
shows the PLL power supply filter circuit.
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
DD
pin being supplied. It should be possible to route directly from the capacitors to the AV
V
DD
DD
DD
DD
Figure 41. PLL Power Supply Filter Circuit
10 Ω
1
, and preferably these voltages are derived directly from V
)
2
generates the platform clock from the externally supplied CLKIN
)
generates the core clock as a slave to the platform clock. The
2.2 µF
Section 19.1, “System PLL Configuration.”
GND
Section 19.2, “Core PLL Configuration.”
Low ESL Surface Mount Capacitors
Figure
2.2 µF
41, one to each of the five AV
DD
AV
1, AV
DD
(or L2AV
DD
2, respectively). The AV
DD
)
Freescale Semiconductor
DD
DD
through a
pins.
DD
DD