mpc8349ea Freescale Semiconductor, Inc, mpc8349ea Datasheet
mpc8349ea
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mpc8349ea Summary of contents
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... MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual. To locate published errata or updates for this document, refer to the MPC8349EA product summary page on our website listed on the back cover of this document or, contact your local Freescale sales office. © Freescale Semiconductor, Inc., 2009. All rights reserved. ...
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... Floating-point, integer, load/store, system register, and branch processing units — 32-Kbyte instruction cache, 32-Kbyte data cache — Lockable portion of L1 cache — Dynamic power management MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev NOTE Arbiter Bus Monitor ...
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... Single 64-bit data PCI interface operating MHz — PCI 3.3-V compatible — PCI host bridge capabilities on both interfaces — PCI agent mode on PCI1 interface — PCI-to-memory and memory-to-PCI streaming MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Overview 3 ...
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... Four crypto-channels, each supporting multi-command descriptor chains – Static and/or dynamic assignment of crypto-execution units through an integrated controller – Buffer size of 256 bytes for each execution unit, with flow control for large data sizes MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Freescale Semiconductor ...
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... Support for 1 external (optional) and 7 internal machine checkstop interrupt sources — Programmable highest priority request — Four groups of interrupts with programmable priority — External and internal interrupts directed to host processor MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Overview 5 ...
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... Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8349EA. The MPC8349EA is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. ...
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... IN REF the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation shown in Figure 3. MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Table 1. Absolute Maximum Ratings Symbol ...
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... Electrical Characteristics 2.1.2 Power Supply Voltage Specification Table 2 provides the recommended operating conditions for the MPC8349EA. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. Table 2. Recommended Operating Conditions Characteristic Core supply voltage for 667-MHz core frequency ...
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... Power Sequencing MPC8349EA does not require the core supply voltage and I/O supply voltages to be applied in any particular order. Note that during the power ramp up, before the power supplies are stable, there may be a period of time that I/O pins are actively driven. After the power is stable, as long as PORESET is asserted, most I/O pins are three-stated ...
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... Power Characteristics 3 Power Characteristics The estimated typical power dissipation for the MPC8349EA device is shown in Core Frequency (MHz) TBGA 333 400 450 500 533 667 1 The values do not include I/O supply power (OV 2 Typical power is based on a voltage of V application. 3 Thermal solutions may need to design to a value higher than typical power based on the end application, T power ...
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... MHz, 32 bits load = MHz, 32 bits 66 MHz, 32 bits 50 MHz, 32 bits TSEC I/O MII load = 25 pF GMII or TBI RGMII or RTBI USB 12 MHz 480 MHz Other I/O MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor (1.8 V) (2.5 V) (3.3 V) (3.3 V) ...
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... PCI_SYNC_IN input current OV PCI_SYNC_IN input current 4.2 AC Electrical Characteristics The primary clock source for the MPC8349EA can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. (CLKIN/PCI_CLK) AC timing specifications for the MPC8349EA. Parameter/Condition CLKIN/PCI_CLK frequency CLKIN/PCI_CLK cycle time ...
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... This section describes the DC and AC electrical specifications for the reset initialization timing and electrical requirements of the MPC8349EA. 5.1 RESET DC Electrical Characteristics Table 8 provides the DC electrical characteristics for the RESET pins of the MPC8349EA. Table 8. RESET Pins DC Electrical Characteristics Characteristic Input high voltage Input low voltage ...
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... CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual . the clock period of the input clock applied to CLKIN valid only in PCI host mode. See the MPC8349EA CLKIN PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual . ...
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... DDR SDRAM component(s) when GV (typ Table 13. DDR SDRAM DC Electrical Characteristics for GV Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor . Symbol Min GV 1.71 DD 0.49 × REF ...
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... AC timing specifications for the DDR2 SDRAM when GV Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface At recommended operating conditions with GV Parameter AC input low voltage AC input high voltage MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev –0 – ...
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... CISKEW 3. This specification applies only to the DDR interface. Figure 4 illustrates the DDR input timing diagram showing the t MCK[n] MCK[n] MDQS[n] MDQ[x] MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor of 2.5 ± 5%. DD Symbol Min V — ...
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... MHz 333 MHz 266 MHz 200 MHz MDQ/MECC/MDM output hold with respect to MDQS 400 MHz 333 MHz 266 MHz 200 MHz MDQS preamble start MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev (1.8 or 2.5 V) ± 5 Symbol Min t DDKHAS 1.95 2 ...
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... DQSS override bits in the TIMING_CFG_2 registerand is typically set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these two parameters are set to the same adjustment value. See the MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual for the timing modifications enabled by use of these bits. ...
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... This section describes the DC and AC electrical specifications for the DUART interface of the MPC8349EA. 7.1 DUART DC Electrical Characteristics Table 20 provides the DC electrical characteristics for the DUART interface of the MPC8349EA. Table 20. DUART DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage Input current (0.8 V ≤ V ≤ ...
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... Low-level output voltage 7.2 DUART AC Electrical Specifications Table 21 provides the AC timing parameters for the DUART interface of the MPC8349EA. Minimum baud rate Maximum baud rate Oversample rate Notes: 1. Actual attainable baud rate will be limited by the latency of interrupt processing. 2. The middle of a start bit is detected as the 8 ...
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... The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section. 8.2.1 GMII Timing Specifications This section describes the GMII transmit and receive AC timing specifications. MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev 23. The RGMII and RTBI signals in Symbol ...
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... This symbol represents the external GTX_CLK125 signal and does not follow the original symbol naming convention. Figure 8 shows the GMII transmit AC timing diagram. GTX_CLK TXD[7:0] TX_EN TX_ER MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor /OV of 3.3 V ± 10 ...
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... GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). Figure 9 shows the GMII receive AC timing diagram. G RX_CLK RXD[7:0] RX_DV RX_ER MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev /OV of 3.3 V ± 10 Symbol t ...
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... MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). Figure 10 shows the MII transmit AC timing diagram. TX_CLK TXD[3:0] TX_EN TX_ER MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor /OV of 3.3 V ± 10 Symbol ...
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... MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). Figure 11 provides the AC test load for TSEC. Output Figure 12 shows the MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev /OV of 3.3 V ± 10 Symbol t MRX t ...
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... This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention Figure 13 shows the TBI transmit AC timing diagram. GTX_CLK TXD[7:0] TX_EN TX_ER MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor /OV of 3.3 V ± 10 ...
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... Setup and hold time of even numbered RCG are measured from the riding edge of PMA_RX_CLK1. Setup and hold times of odd-numbered RCG are measured from the riding edge of PMA_RX_CLK0. Figure 14 shows the TBI receive AC timing diagram. PMA_RX_CLK1 RCG[9:0] PMA_RX_CLK0 MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev /OV of 3.3 V ± 10 ...
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... Duty cycle reference This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention. MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Specifications of 2.5 V ± 5%. DD ...
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... MDIO and MDC are provided in Table 31. MII Management DC Electrical Characteristics Powered at 2.5 V Parameter Supply voltage (2.5 V) Output high voltage Output low voltage Input high voltage Input low voltage MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev RGTH t SKRGT TXD[8:5] TXD[3:0] ...
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... At recommended operating conditions with LV Parameter/Condition MDC frequency MDC period MDC clock pulse width high MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Symbol Conditions ...
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... MHz, the delay is 58 ns). Figure 16 shows the MII management AC timing diagram. MDC MDIO (Input) MDIO (Output) Figure 16. MII Management Interface Timing Diagram MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev 3.3 V ± 10% or 2.5 V ± 5 Symbol Min t — ...
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... USB This section provides the AC and DC electrical specifications for the USB interface of the MPC8349EA. 9.1 USB DC Electrical Characteristics Table 34 provides the DC electrical characteristics for the USB interface. Parameter High-level input voltage Low-level input voltage Input current = –100 μA High-level output voltage 100 μ ...
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... Parameter High-level input voltage Low-level input voltage Input current = –100 μA High-level output voltage 100 μA Low-level output voltage MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Ω Ω Figure 17. USB AC Test Load t USIVKH ...
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... LBOTOT3 output pins. 8. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification. MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 1 Symbol ...
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... DLL bypass mode is not recommended for use at frequencies above 66 MHz. Figure 19 provides the AC test load for the local bus. Output MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Symbol t ...
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... LAD[0:31]/LDP[0:3] Input Signal: LGTA Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE Output Signals: LAD[0:31]/LDP[0:3] LALE Figure 21. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode) MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor t LBIVKH t LBKHOV t LBKHOZ t t LBKHOV ...
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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 23. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev LBKHOZ1 t LBKHOV1 t LBIVKH2 ...
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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 24. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor t LBKHOZ t LBKLOV t LBIVKH ...
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... DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the MPC8349EA. Table 39. JTAG Interface DC Electrical Characteristics Characteristic Input high voltage Input low voltage Input current Output high voltage MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev LBKHOZ1 t LBKHOV1 t LBIVKH2 ...
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... JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data Input hold times: Boundary-scan data Valid times: Boundary-scan data Output hold times: Boundary-scan data MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Symbol Condition 8 ...
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... Non-JTAG signal input timing with respect Non-JTAG signal output timing with respect Guaranteed by design and characterization. Figure 26 provides the AC test load for TDO and the boundary-scan outputs of the MPC8349EA. Output Figure 26. AC Test Load for the JTAG Interface Figure 27 provides the JTAG clock input timing diagram ...
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... JTAG External Clock TDI, TMS t JTKLOX TDO TDO Output Data Valid Figure 30. Test Access Port Timing Diagram MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor VM t JTDVKH t JTKLDV t JTKLDZ VM = Midpoint Voltage (OV DD /2) Figure 29 ...
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... Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current capacitance of one bus line in pF Refer to the MPC8349EA Integrated Host Processor Family Reference Manual, for information on the digital filter used. 4. I/O pins obstruct the SDA and SCL lines 12.2 I ...
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... For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). 2. MPC8349EA provides a hold time of at least 300 ns for the SDA signal (referred to the V the undefined region of the falling edge of SCL. ...
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... IN 13.2 PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus of the MPC8349EA. Note that the PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8349EA is configured as a host or agent device. Table 44. PCI AC Timing Specifications at 66 MHz ...
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... For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. 5. The setup and hold time is with respect to the rising edge of PORESET. MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 2 Symbol ...
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... Timers This section describes the DC and AC electrical specifications for the timers. 14.1 Timer DC Electrical Characteristics Table 46 provides the DC electrical characteristics for the MPC8349EA timer pins, including TIN, TOUT, TGATE, and RTC_CLK. Table 46. Timer DC Electrical Characteristics Characteristic Input high voltage Input low voltage ...
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... DC electrical characteristics for the MPC8349EA GPIO. Table 48. GPIO DC Electrical Characteristics Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Symbol Condition 8 ...
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... Input specifications are measured at the 50 percent level of the IPIC input signals. Timings are measured at the pin. 2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by external synchronous logic. IPIC inputs must be valid for at least t MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev ensure proper operation. ...
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... SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X). MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Table 52. SPI DC Electrical Characteristics Symbol ...
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... Input Signals: SPIMISO (See Note) Output Signals: SPIMOSI (See Note) Note: The clock edge is selectable on SPI. Figure 38. SPI AC Timing in Master Mode (Internal Clock) Diagram MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Ω Figure 36. SPI AC Test Load Table 53 ...
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... Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8349EA is available in a tape ball grid array (TBGA). See Section 18.2, “Mechanical Dimensions for the MPC8349EA 18.1 Package Parameters for the MPC8349EA TBGA The package parameters are provided in the following list. The package type × 35 mm, 672 tape ball grid array (TBGA) ...
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... Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5. Parallelism measurement must exclude any effect of mark on top surface of package. Figure 39. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC8349EA TBGA MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 ...
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... PCI1_GNT1/CPCI1_HS_LED PCI1_GNT2/CPCI1_HS_ENUM PCI1_GNT[3:4] PCI2_RESET_OUT/GPIO2[0] PCI2_AD[31:0]/PCI1[63:32] PCI2_C/BE[3:0]/PCI1_C/BE[7:4] PCI2_PAR/PCI1_PAR64 MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Package Pin Number PCI1 and PCI2 (One 64-Bit or Two 32-Bit) B34 C33 G30, G32, G34, H31, H32, H33, H34, J29, ...
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... MECC[6:7] MDM[0:8] MDQS[0:8] MBA[0:1] MA[0:14] MWE MRAS MCAS MCS[0:3] MCKE[0:1] MCK[0:5] MCK[0:5] MODT[0:3] MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Package Pin Number AE33 AF32 AE34 AF34 AF33 AG33 AG32 Y32, Y34, AA32 Y31, Y33, AA31 A19 DDR SDRAM Memory Interface ...
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... LCKE LCLK[0:2] LSYNC_OUT LSYNC_IN GPIO1[0]/DMA_DREQ0/GTM1_TIN1/ GTM2_TIN2 GPIO1[1]/DMA_DACK0/ GTM1_TGATE1/GTM2_TGATE2 MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Package Pin Number H4 AB1 AA1 Local Bus Controller Interface AM13, AP13, AL14, AM14, AN14, AP14, AK15, AJ15, AM15, AN15, AP15, AM16, ...
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... MPH1_D2_VMO_SE0/ DR_D2_VMO_SE0 MPH1_D3_SPEED/DR_D3_SPEED MPH1_D4_DP/DR_D4_DP MPH1_D5_DM/DR_D5_DM MPH1_D6_SER_RCV/ DR_D6_SER_RCV MPH1_D7_DRVVBUS/ DR_D7_DRVVBUS MPH1_NXT/DR_SESS_VLD_NXT MPH1_DIR_DPPULLUP/ DR_XCVR_SEL_DPPULLUP MPH1_STP_SUSPEND/ DR_STP_SUSPEND MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Package Pin Number B25 D24 A25 B24 A24 D23 B23 A23 F22 E22 USB Port 1 A26 ...
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... MPH0_PWRFAULT/DR_RX_VALIDH MPH0_PCTL0/DR_LINE_STATE0 MPH0_PCTL1/DR_LINE_STATE1 MPH0_CLK/DR_RX_VALID MCP_OUT IRQ0/MCP_IN/GPIO2[12] IRQ[1:5]/GPIO2[13:17] IRQ[6]/GPIO2[18]/CKSTOP_OUT IRQ[7]/GPIO2[19]/CKSTOP_IN EC_MDC EC_MDIO MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Package Pin Number E27 A29 D28 B29 USB Port 0 C29 A30 E28 B30 ...
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... TSEC2_RXD[7:4]/GPIO1[26:29] TSEC2_RXD[3:0]/GPIO1[13:16] TSEC2_RX_ER/GPIO1[25] TSEC2_TXD[7]/GPIO1[31] TSEC2_TXD[6]/ DR_XCVR_TERM_SEL TSEC2_TXD[5]/ DR_UTMI_OPMODE1 TSEC2_TXD[4]/ DR_UTMI_OPMODE0 TSEC2_TXD[3:0]/GPIO1[17:20] MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Package Pin Number Gigabit Reference Clock C8 A17 F12 D10 A11 B11 B17 B16, D16, E16, F16 ...
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... SPIMISO/LCS[7] SPICLK SPISEL PCI_CLK_OUT[0:2] PCI_CLK_OUT[3]/LCS[6] PCI_CLK_OUT[4]/LCS[7] PCI_CLK_OUT[5:7] PCI_SYNC_IN/PCI_CLOCK PCI_SYNC_OUT RTC/PIT_CLOCK CLKIN TCK TDI MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Package Pin Number F14 C5 E14 DUART AK27, AN29 AL28, AM29 AP30 AN30 AP31, AM30 2 ...
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... QUIESCE PORESET HRESET SRESET THERM0 MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Package Pin Number B20 A20 B19 Test D22 AL13 PMC A18 System Control C18 B18 D18 Thermal Management K32 ...
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... DD2 MVREF1 MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Package Pin Number A1, A34, C1, C7, C10, C11, C15, C23, C25, C28, D1, D8, D20, D30, E7, E13, E15, E17, E18, E21, E23, E25, E32, F6, F19, F27, F30, F34, G31, H5, J4, J34, ...
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... For proper functionality of the device, this pin must be pulled up or actively driven high during a hard reset. No external pull-down resistors are allowed to be attached to this net. MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev ...
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... PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN, with equal delay to all PCI agent devices in the system, to allow the MPC8349EA to function. When the MPC8349EA is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN signal should be tied to GND. MPC8349EA PowerQUICC™ ...
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... SPMF and COREPLL fields in the reset configuration word low (RCWL), which is loaded at power-on reset or by one of the hard-coded reset options. See the chapter on reset, clocking, and initialization in the MPC8349EA Reference Manual for more information on the clock subsystem. ...
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... RCWL[LBIUCM]). 19.1 System PLL Configuration The system PLL is controlled by the RCWL[SPMF] parameter. encodings for the system PLL. MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Table 56. Operating Frequencies for TBGA 400 MHz 266–400 100– ...
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... Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev System PLL Multiplication RCWL[SPMF] Factor 1010 × 10 1011 × 11 1100 × 12 1101 × 13 1110 × 14 1111 × ...
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... Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low High MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor csb_clk : SPMF Input Clock 16.67 2 Ratio 0010 0011 0100 0101 0110 ...
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... MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev csb_clk : SPMF Input Clock 16.67 2 Ratio 0011 100 0100 133 0101 166 0110 200 ...
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... MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor core_clk : csb_clk Ratio 2:1 2:1 2:1 2:1 2.5:1 2.5:1 2.5:1 2.5:1 3:1 3:1 3:1 3:1 Table 61. Suggested PLL Configurations 533 MHz Device Input CSB Core ...
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... MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev 533 MHz Device Input CSB Core CSB Clock Freq Freq Freq Freq (MHz) (MHz) (MHz) 2 (MHz) — ...
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... The input clock is CLKIN for PCI host mode or PCI_CLK for PCI agent mode. 20 Thermal This section describes the thermal specifications of the MPC8349EA. 20.1 Thermal Characteristics provides the package thermal characteristics for the 672 35 × TBGA of the MPC8349EA. Table 62 Table 62. Package Thermal Characteristics for TBGA Characteristic Junction-to-ambient natural convection on single-layer board (1s) ...
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... The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev × I ...
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... Some application environments require a heat sink to provide the necessary thermal management of the device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance θ JA MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor × θ Ψ ...
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... More detailed thermal models can be made available on request. MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev For instance, the user can change the size of the heat θ ...
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... Internet: www.chomerics.com Dow-Corning Corporation Dow-Corning Electronic Materials P.O. Box 994 Midland, MI 48686-0997 Internet: www.dowcorning.com Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 603-224-9988 408-567-8082 818-842-7277 408-436-8770 800-522-2800 603-635-5102 781-935-4850 800-248-2481 ...
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... The platform PLL generates the platform clock from the externally supplied CLKIN input. The frequency ratio between the platform and CLKIN is selected using the platform PLL ratio configuration bits as described in MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev × P ...
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... Decoupling Recommendations Due to large address and data buses and high operating frequencies, the MPC8349EA can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8349EA system, and the MPC8349EA itself requires a clean, tightly regulated source of power ...
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... MPC8349EA. 21.5 Output Buffer DC Impedance The MPC8349EA drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I To measure Z for the single-ended drivers, an external resistor is connected from the chip pad GND ...
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... Pull-Up Resistor Requirements The MPC8349EA requires high resistance pull-up resistors (10 kΩ is recommended) on open-drain pins, 2 including I C pins, the Ethernet Management MDIO pin, and IPIC interrupt pins. ...
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... Options,’ added row 503 between Ref. No. 305 and 404. For Ref. No. 306, changed the CORE PLL value to 0000110. In Section 23, “Ordering Information,” replaced first paragraph and added a note. In Section 23.1, “Part Numbers Fully Addressed by This Document,” replaced first paragraph. MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Table 65. Document Revision History Substantive Change(s) Clocking,” ...
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... Specifications,” rows 2 and 3, and in Figure 2, “DDR SDRAM Output Timing Diagram. Changed Min and Max values for V In Table 55, “MPC8349EA (TBGA) Pinout Listing,” modified rows for MDICO and MDIC1 signals and added note “It is recommended that MDICO be tied to GRD using an 18 Ω resistor and MCIC1 be tied to DDR power using an 18 Ω ...
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... Each part number also contains a revision code that refers to the die mask revision number. For available frequency configuration parts including extended temperatures, refer to the MPC8349EA product summary page on our website listed on the back cover of this document or, contact your local Freescale sales office. ...
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... Part Marking Parts are marked as in the example shown in Figure 43. Freescale Part Marking for TBGA Devices MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Figure 43. MPCnnnnetppaaar core/platform MHZ ATWLYYWW CCCCC *MMMMM YWWLAZ TBGA Notes : ATWLYYWW is the traceability code. ...
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... Ordering Information THIS PAGE INTENTIONALLY LEFT BLANK MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Freescale Semiconductor ...
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... THIS PAGE INTENTIONALLY LEFT BLANK MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Ordering Information 87 ...
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... Denver, Colorado 80217 1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8349EAEC Rev. 10 05/2009 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...