mpc8349ea Freescale Semiconductor, Inc, mpc8349ea Datasheet - Page 82

• Manufacturer Part Number: mpc8349ea
• Description: Mpc8349ea Powerquicc
• Manufacturer: Freescale Semiconductor, Inc

Document Revision History
22 Document Revision History
Table 65
82
Revision
10
9
8
7
provides a revision history of this document.
MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
5/2009
2/2009
4/2007
3/2007
Date
In
DDR2.
In
core frequency = 533MHz.
In
PBGA from 95.5 Sn/0.5 Cu/4 Ag to 96.5 Sn/3.5 Ag.
In
In
independent filter circuits,” and “the five AVDD pins” to provide four independent filter circuits,” and “the
four AVDD pins.”
In
In
In
DLL bypass mode). Similarly, made the same correction to
output signals.
In
Added footnote 4 to
In
limited to 533 with a platform frequency of 266.”
Added footnote 11 to
In
Added footnote 6 to
In
In
USB to the seventh row.
In
paragraph, added a new paragraph.
Deleted Section 21.8, “JTAG Configuration Signals,” and Figure 43, “JTAG Interface Connection.”
In Table 57, “Operating Frequencies for TBGA,” in the ‘Coherent system bus frequency ( csb_clk )’ row,
changed the value in the 533 MHz column to 100-333.
In Table 63, “Suggested PLL Configurations,” under the subhead, ‘33 MHz CLKIN/PCI_CLK Options,’
added row A03 between Ref. No. 724 and 804. Under the subhead ‘66 MHz CLKIN/PCI_CLK
Options,’ added row 503 between Ref. No. 305 and 404. For Ref. No. 306, changed the CORE PLL
value to 0000110.
In Section 23, “Ordering Information,” replaced first paragraph and added a note.
In Section 23.1, “Part Numbers Fully Addressed by This Document,” replaced first paragraph.
Table
Section 18.1, “Package Parameters for the MPC8349EA
Table
Table
Table
Section 21.1, “System
Section 21.2, “PLL Power Supply
Table
Table
Table
Table
Table
Table
resistor. For proper functionality of the device, this pin must be pulled up or actively driven high
during a hard reset. No external pull-down resistors are allowed to be attached to this net.”
input frequency down-spread at maximum 50KHz modulation rate regardless of input frequency.”
Section 21.7, “Pull-Up Resistor Requirements,”
66, footnote 1, changed 667(TBGA) to 533(TBGA). footnote 4, added data rate for DDR1 and
7, updated the note 6 to say the following: “The Spread spectrum clocking. Is allowed with 1%
66, updated note 1 to say the following: “For temperature range = C, processor frequency is
3,
56, updated frequecy for max csb_clk to 333 MHz and DDR2, from 100-200 to 100-133 at
52, corrected the max csb_clk to 266 MHz.
57, added PLL configurations 903, 923, A03, A23, and 503 for 533 MHz
34, corrected t
9.2, clarified that AC table is for ULPI only.
54, updated note 11 to say the following: “SEC1_TXD[3] is required an external pull-up
“Output Drive Capability,”
Table 65. Document Revision History
Table
Table
Table
LBKHOV
Clocking,” removed “(AVDD1)” and “(AVDD2”) from bulleted list.
66.
7.
54.
parametr to t
Filtering,” in the second paragraph, changed “provide five
changed the values in the Output Impedance column and added
Substantive Change(s)
LBKLOV
deleted last two paragraphs and after first
(output data is driven on falling edge of clock in
TBGA, changed solder ball for TBGA and
Figure
16,
Figure
Freescale Semiconductor
18, and
Figure 19
for