mpc89x51a Megawin Technology, mpc89x51a Datasheet
mpc89x51a
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mpc89x51a Summary of contents
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... DC Characteristics (MPC89L51A)...................................................................................... 35 Package Dimension.............................................................................................................. 36 Revision History .................................................................................................................. 39 This document contains information on a new product under development by Megawin. Megawin reserves the right to change or discontinue this product without notice. © Megawin Technology Co., Ltd. 2004 All right reserved. MPC89x51A 8-bit micro-controller 2007/12 version A10 MEGAWIN ...
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... MPC89L51A, minimum 2.7V requirement in flash write operation (ISP/ICP/…...) - Built-in Low-Voltage-Reset circuit. Operating Temperature - Industrial (-40°C to +85°C)* Maximum Operating Frequency: - Optional 12T or 6T mode - Up to 48MHz@12T or 24MHz@6T, Industrial range Three package types: - PDIP 40: MPC89x51AE - PLCC 44: MPC89x51AP - PQFP 44: MPC89x51AF 2 MPC89x51A Data Sheet MEGAWIN ...
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... Tested by sampling MEGAWIN MPC89x51A Data Sheet 3 ...
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... The user can configure the device to run in 12 clocks per machine cycle clocks per machine cycle to achieve twice performance. MPC89x51A is built with four 8-bits I/O ports, one 4-bits I/O ports, three 16-bits timer/counters, an eight-source, four-priority-level interrupt structure, an enhanced UART and on-chip crystal oscillator ...
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... BU General-purposed I/O with weak pull-up resistance inside. When 1s are written 7 into Port1, the strong output driving 8 PMOS only turn-on two clock periods 9 and then the weak pull-up resistance 10 MPC89x51A Data Sheet Description also used as one of emits the high-order 5 ...
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... EA must be kept at low to enable the device to fetch program code from external flash memory. An internal pull-up resistance has been embedded in this pin Input to the inverting oscillator amplifier Output from the inverting amplifier Power Supply 16 G Ground MPC89x51A Data Sheet MEGAWIN ...
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... MPC89x51AF (PQFP-44 MPC89x51A Data Sheet P0.4 (AD4) 38 P0.5 (AD5) 37 P0.6 (AD6) 36 P0.7 (AD7) 35 /EA MPC89x51AP 34 (PLCC-44) 33 ALE 32 /PSEN 31 P2.7 (A15) 30 P2.6 (A14) 29 P2.5 (A13 ...
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... RAM256 Stack Pointer TMP2 TMP1 ALU PSW WDT Port1 Latch Port3 Latch Port1 Driver Port3 Driver XTAL2 P1.0 ~ P1.7 P3.0 ~ P3.7 MPC89x51A Block Diagram MPC89x51A Data Sheet P0.0 ~ P0.7 Port0 Driver Port0 Latch Flash ROM ISP Timer0/1 Address Timer2 Generator UART Program Counter DPTR Port4 Latch ERAM Port4 Driver P4 ...
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... TF2 EXF2 RCLK TCLK EXEN2 TR2 RS1 RS0 - - ENW CLW WIDL - - - - - ISPEN BS SRST - - - - - - EBH MPC89x51A Data Sheet IFMT SCMD ISPCR TH2 IPH TH1 AUXR PCON INITIAL VALUE 11111111B 00000111B 00000000B 00000000B GF0 PD IDL 01110000B IT1 IE0 IT0 00000000B C// 00000000B ...
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... Memory Organization Address Space for MPC89x51A RAM Address Space for MPC89x51A embedded Flash memory Bits-7 Bits-6 Bits-5 ISPAS1 FZWDTCR 10 00-7F RAM, Access it via direct addressing 80-FF SFR, Access it via direct addressing 80-FF indirect on-chip RAM, Access it via indirect addressing 00-FF on-chip expanded RAM (256B), ...
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... Nonvolatile Registers: There are two Nonvolatile Registers named OR0 and OR1 individually. They are designed to configure the MPC89x51A options. Generally these two nonvolatile registers will be written via a popular NVM writer, say Hi-Lo System All-11, Leaper-48 and Megawin-Provided MCU writer. Furthermore, the user can change the NVM register OR1 by the ISP program in a manner as same as writing the data flash, but OR0 can only be written via an off-line popular NVM writer ...
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... It is recommended to do so. 1:= The gained of crystal oscillator is enough for oscillator to start oscillating MHz. HWBS: Used to configure the MPC89x51A boot from ISP program or normal application program after the power-on sequence. 0:= The MPC89x51A will boot from ISP start address after power-on. ...
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... The leading 4 K bytes flash memory is designed for storage of the user program, followed 11 K bytes flash memory is shared with nonvolatile data flash and ISP program. While the program counter of MPC89x51A is spanning over 0FFFh, the device will fetch its program code from the external memory at once ignoring the /EA pin status. In that case, it will never fetch the program code from the following embedded flash ...
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... Functional Description TIMERS/COUNTERS MPC89x51A has three 16-bits timers, and they are named T0, T1 and T2.Each of them can also be used as a general event counter, which counts the transition from While T0/T1/T2 is used as “timer” function, the time unit that used to measure the timer is machine cycle ...
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... EXEN2=0 causes Timer2 to ignore events at T2EX. TR2: Start/Stop control for Timer2. MEGAWIN Bits-4 Bits-3 Bits-2 Bits-1 TR0 IE1 IT1 IE0 Bits-4 Bits-3 Bits-2 Bits-1 T2OE Bits-4 Bits-3 Bits-2 Bits-1 TCLK EXEN2 TR2 C//T2 MPC89x51A Data Sheet Bits-0 IT0 Bits-0 DCEN Bits-0 CP/RL2 15 ...
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... Overflow from TLx does not only set TFx, but also reloads TLx with the content of THx, which is determined by user’s program. The reload leaves THx unchanged. Mode 2 operation is the same for Timer0 and Timer1 TLx[4:0] THx[7: TLx[7:0] THx[7:0] 1 MPC89x51A Data Sheet TFx Interrupt Mode 0 TFx Interrupt Mode 1 MEGAWIN ...
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... MEGAWIN 0 TLx [7:0] 1 THx [7:0] 0 TL0 [7:0] 1 TH0 [7:0] TR2 DCEN 0 x OFF 1 0 Baud-Rate Generation 1 0 Capture 1 0 Auto-Reload Up-only 1 1 Auto-Reload Up/Down Timer2 Mode Table MPC89x51A Data Sheet Interrupt TFx Reload Mode 2 Interrupt TF0 Mode 3 Interrupt TF1 Mode 17 ...
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... Timer2 is also can be configured as a periodical signal generator. The MPC89x51A is able to generate a programmable clock output on P1.0. When T2OE bits is set and C//T2 bits is cleared, Timer2 overflow pulse will generate a 50% duty clock and output that to P1.0. The frequency of clock-out is calculated according to the following formula. ...
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... DOWN, the overflow loads 0xFFFF onto Timer2, and if counting direction is UP, the overflow loads RCAP2H, RCAP2L contents onto Timer2 OSC/ pin 1 C//T2 TR2 MEGAWIN 0 TL2 [7:0] TH2[7:0] 1 RCAP2L [7:0] RCAP2H [7:0] FFH FFH TL2 [7:0] TH2[7:0] RCAP2L [7:0] RCAP2H [7:0] MPC89x51A Data Sheet TF2 Interrupt EXF2 EXF2 TF2 Interrupt T2EX pin 19 ...
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... T2 pin C//T2 TR2 T2EX pin EXEN2 20 16 Oscillator Frequency TL2[7:0] TH2[7:0] RCAP2L[7:0] RCAP2H[7:0] EXF2 Timer2 interrupt MPC89x51A Data Sheet (counting T2EX) (as a timer) Timer1 overflow 2 “0” “1” SMOD “1” “0” RCLK 16 “1” “0” TCLK RX Clock ...
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... Interrupt There are eight interrupt sources available in MPC89x51A. Each interrupt source can be individually enabled or disabled by setting or clearing a bits in the SFR named IE. This register also contains a global disable bits (EA), which can be cleared to disable all interrupts at once. Each interrupt source has two corresponding bits to represent its priority. One is located in SFR named IPH and the other in IP/XICON register ...
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... PT0H: If set, Set priority for timer0 interrupt highest PX0H: If set, Set priority for external interrupt 0 highest 22 Bits-4 Bits-3 Bits-2 ES ET1 EX1 Bits-4 Bits-3 Bits-2 PS PT1 PX1 Bits-4 Bits-3 Bits-2 PSH PT1H PX1H MPC89x51A Data Sheet Bits-1 Bits-0 ET0 EX0 Bits-1 Bits-0 PT0 PX0 Bits-1 Bits-0 PT0H PX0H MEGAWIN ...
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... IT2: Interrupt 2 types control bits. Set/Cleared by software to specify falling edge/low level triggered interrupt. Watchdog Timer CLK/12 ENW 8-bit pre-scalar timer IDLE WIDL CLRW MEGAWIN Priority Level 1 (highest Bits-4 Bits-3 Bits-2 IT3 PX2 EX2 8 PS0 PS1 PS2 MPC89x51A Data Sheet Bits-1 Bits-0 IE2 IT2 15-bit WDT RESET 23 ...
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... Serial IO Port (UART) The serial port of MPC89x51A is duplex. It can transmit and receive simultaneously. The receiving and transmitting of the serial port share the same SFR SBUF, but actually there are two SBUF registers implemented in the chip, one is for transmitting and the other is for receiving ...
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... Mode 3 MEGAWIN th bits and a stop bits (1). On transmit, SMOD SMOD (Timer-1 overflow rate) 32 (Timer-2 overflow rate Bits-4 Bits-3 Bits-2 REN TB8 RB8 MPC89x51A Data Sheet th data bits goes into RB8 in osc Bits-1 Bits ...
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... RI in SFR SCON. Normally, an UART will set bits RI whenever it has done a bytes reception; but for the UART in the MPC89x51A, if the bits SM2 is set, it will set RI according to the following formula (SM2 == 1) && (SBUF == Compared Byte) && (RB8 == 1) ...
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... Any positive pulse from RESET pin must be kept at least two-machine cycle, or the device cannot be reset. Power Saving Mode and POF There are two power saving modes which are selectable to drive the MPC89x51A to enter power-saving mode. 1. IDLE mode The user can set the bits PCON.0 to drive this chip entering IDLE mode. ...
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... Unlike RAM’s real-time operation, to erase flash or to write (program) flash often takes longer time to finish. 28 ALE PSEN Port0 1 1 Data 1 1 Float 0 0 Data 0 0 Float MPC89x51A Data Sheet Port1 Port2 Port3 Data Data Data Data Address Data Data Data Data Data Data Data MEGAWIN ...
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... Furthermore quite complex timing procedure to erase/program flash. Fortunately, the MPC89x51A carried with convenient mechanism to help the user read/change the flash content. Just filling the target address and data into several SFR, and triggering the built-in ISP automation, the user can easily erase, read, and program the embedded flash and option registers OR1 ...
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... SCMD is the command port for triggering ISP activity. If SCMD is filled with sequential 46h, B9h and if ISPCR ISP activity will be triggered. When this register is read, the device ID of MPC89x51A will be returned (2 bytes). The MSB bytes of DID is F0h and LSB bytes 01h. IFADRL[0] is used to select HIGH/LOW bytes of DID. ...
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... SCMD ← B9h (CPU progressing will be hold here) (CPU continues and currently IFD contain the desired data byte ) Booting Program Entrance The MPC89x51A boots according to the following rule HWBS == 0 ) System will boot from ISP program else System will boot from normal AP program Above rule is adaptive only for power-up procedure, not software reset ...
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... Note : Even the users do not need ISP space, the OR0[5:4] still needs to be programmed with {10} if IAP data flash is desired. In other words, the maximum available size in data flash for IAP operation is 10K bytes MPC89x51A Data Sheet MEGAWIN ...
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... ALE is active only during access to external memory for both MOVC and MOVX SFR: AUXR1 Bits-7 Bits-6 Bits GF2: General purpose flag DPS: Data pointer switch 0: = Make the data pointer-0 active 1: = Make the data pointer-1 active MEGAWIN Bits-4 Bits-3 Bits Bits-4 Bits-3 Bits-2 - GF2 - MPC89x51A Data Sheet Bits-1 Bits-0 ERAM AO Bits-1 Bits-0 - DPS 33 ...
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... Power down current PD Rrst Internal pull-down resistance in RESET 34 (MPC89E51A) - 150 -0.5 ~ VCC + 0.5 (MPC89E51A) Test Condition Vcc=5.0V Vcc=5.0V Vcc =5.0V Vcc=5.0V Vcc=5.0V Vcc=5.0V Vcc = 5.0V Vcc = 5.0V Vpin=0V Vpin=2.0V Vcc=5.0V Vcc=5.0V Vcc=5.0V MPC89x51A Data Sheet Rating Unit °C -55 ~ +125 °C V -0.5 ~ +6.0 V 500 Specification Min. Typ. Max. 0.8 1.6 2.0 3 ...
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... Power down current PD Rrst Internal pull-down resistance in RESET MEGAWIN (MPC89L51A) - 150 -0.3 ~ VCC + 0.3 (MPC89L51A) Test Condition Vcc=3.3V Vcc=3.3V Vcc =3.3V Vcc=3.3V Vcc=3.3V Vcc=3.3V Vcc = 3.3V Vcc =3.3V Vpin=0V Vpin=2.0V Vcc=3.3V Vcc=3.3V Vcc=3.3V MPC89x51A Data Sheet Rating Unit °C -55 ~ +125 °C V -0.3 ~ +4.2 V 500 Specification Min. Typ. Max. 0.8 1.5 2.0 3.0 2.5 4 ...
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... Package Dimension 40-pin PDIP (MPC89x51AE) 36 MPC89x51A Data Sheet MEGAWIN ...
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... PLCC (MPC89x51AP) MEGAWIN MPC89x51A Data Sheet 37 ...
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... PQFP (MPC89x51AF) 38 MPC89x51A Data Sheet MEGAWIN ...
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... Update PQFP-44 package shape - Modify pin /EA location for PDIP and PLCC package - Modify bits definition for SFR PCON - Absolute Maximum Rating - Revises the possible operating temperature. - Modify the Storage Temperature - Add 2.7V requirement in flash write operation. - Modify Absolute Maximum Rating. MPC89x51A Data Sheet 39 ...