mpc89x51a Megawin Technology, mpc89x51a Datasheet - Page 12

• Manufacturer Part Number: mpc89x51a
• Description: 8-bit Micro-controller
• Manufacturer: Megawin Technology

FZWDTCR: Used to freeze the WDT-controlling register.
OSCDN: Used to adjust the behavior of crystal oscillator.
HWBS: Used to configure the MPC89x51A boot from ISP program or normal application program after
EN6T: Used to configure the MPC89x51A run in 6T 12T mode or 6T mode.
The default value of the OR1 is FFh.
RAM
NVM register: OR1 (Option Register 1):
There are 512 bytes RAM built in MPC89x51A.
The user can visit the leading 128-bytes RAM via direct addressing instructions, we have
named those RAM as direct RAM that occupies address space 00h to 7Fh.
Followed 128-bytes RAM can be visited via indirect addressing instructions, we have named
those RAM as indirect RAM that occupied address space 80h to FFh.
The other 256-bytes RAM is named expanded RAM that still occupied address space 00h to
FFh. An user can access it via general register Ri, or via data pointers DPTR associated with
MOVX instructions, say
characteristic of instruction MOVX which is designed to access external memory, the user can
set the bits ERAM in SFR AUXR as 1, and by doing so is to hide the expanded RAM and to
visit the external memory.
FZWDTCR
12
Bits-7
0:= The MPC89x51A will run in 6T mode
1:= The MPC89x51A will run in 12T mode
the power-on sequence.
0:= The MPC89x51A will boot from ISP start address after power-on.
1:= No operation. The MPC89x51A will boot from normal application program.
1:= The gained of crystal oscillator is enough for oscillator to start oscillating up to 48 MHz.
0:= The DC gained of crystal oscillator amplifier is doubled but bandwidth is reduced. It will bring
1:= (default) Permit all the reset events from power-up, software and the Watch Dog Timer
0:= Configure the SFR WDTCR to be reset only via power-up action; not by software
help to EMI reducing and improve the power consumption. Dealing with application, it does
not need high frequency clock (under 20MHz). It is recommended to do so.
Bits-6
could reset the SFR WDTCR.
reset nor reset from the Watch Dog Timer.
Bits-5
MOVX
OSCDN
MPC89x51A Data Sheet
Bits-4
A, @R1
or
Bits-3
MOVX
Bits-2
A, @DPTR
HWBS
. To reserve the natural
Bits-1
Bits-0
EN6T
MEGAWIN