mpc5632m Freescale Semiconductor, Inc, mpc5632m Datasheet - Page 13

• Manufacturer Part Number: mpc5632m
• Description: Mpc5634m Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

The CPU includes support for Variable Length Encoding (VLE) instruction enhancements. This enables the classic Power
Architecture instruction set to be represented by a modified instruction set made up from a mixture of 16- and 32-bit
instructions. This results in a significantly smaller code size footprint without noticeably affecting performance. The classic
Power Architecture instruction set and VLE instruction set are available concurrently. Regions of the memory map are
designated as PPC or VLE using an additional configuration bit in each of Table Look-aside Buffers (TLB) entries in the MMU.
The CPU core is enhanced by the addition of two additional interrupt sources; Non-Maskable Interrupt and Critical Interrupt.
These two sources are routed directly from package pins, via edge detection logic in the SIU to the CPU, bypassing completely
the Interrupt Controller. Once the edge detection logic is programmed, it cannot be disabled, except by reset. The non-maskable
Interrupt is, as the name suggests, completely un-maskable and when asserted will always result in the immediate execution of
the respective interrupt service routine. The non-maskable interrupt is not guaranteed to be recoverable. The Critical Interrupt
is very similar to the non-maskable interrupt, but it can be masked by other exceptional interrupts in the CPU and is guaranteed
to be recoverable (code execution may be resumed from where it stopped).
The CPU core has an additional ‘Wait for Interrupt’ instruction that is used in conjunction with low power STOP mode. When
Low Power Stop mode is selected, this instruction is executed to allow the system clock to be stopped. An external interrupt
source or the system wake-up timer is used to restart the system clock and allow the CPU to service the interrupt.
1.3.2
The XBAR multi-port crossbar switch supports simultaneous connections between three master ports and four slave ports. The
crossbar supports a 32-bit address bus width and a 64-bit data bus width.
The crossbar allows three concurrent transactions to occur from the master ports to any slave port; but each master must access
a different slave. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher
priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher
priority master completes its transactions. Requesting masters are treated with equal priority and are granted access to a slave
port in round-robin fashion, based upon the ID of the last master to be granted access. The crossbar provides the following
features:
1.3.3
The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data
movements via 32 programmable channels, with minimal intervention from the host processor. The hardware micro architecture
includes a DMA engine which performs source and destination address calculations, and the actual data movement operations,
along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation
is utilized to minimize the overall block size. The eDMA module provides the following features:
Freescale Semiconductor
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3 master ports:
— e200z335 core complex Instruction port
— e200z335 core complex Load/Store port
— eDMA
— FLASH
— calibration bus
— SRAM
— Peripheral bridge A/B (eTPU, eMIOS, SIU, DSPI, eSCI, FlexCAN, eQADC, BAM, decimation filter, PIT, STM
32-bit internal address, 64-bit internal data paths
All data movement via dual-address transfers: read from source, write to destination
Programmable source and destination addresses, transfer size, plus support for enhanced addressing modes
Transfer control descriptor organized to support two-deep, nested transfer operations
4 slave ports
and SWT)
Crossbar
eDMA
Preliminary—Subject to Change Without Notice
MPC5634M Microcontroller Data Sheet, Rev. 3
Overview
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