mpc5632m Freescale Semiconductor, Inc, mpc5632m Datasheet - Page 90

no-image

mpc5632m

Manufacturer Part Number
mpc5632m
Description
Mpc5634m Microcontroller Data Sheet
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Electrical Characteristics
90
1
2
3
4
5
6
7
Num
All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad
types of S or SH have an additional delay based on the slew rate. DSPI timing is specified at VDDEH = 3.0–5.25 V,
TA = TL to TH, and CL = 50 pF with SRC = 0b11.
Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency
modulation (FM). 42 MHz parts allow for 40 MHz system clock + 2% FM; 62 MHz parts allow for a 60 MHz system
clock + 2% FM, and 82 MHz parts allow for 80 MHz system clock + 2% FM.
The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are
calculated based on two MPC5634M devices communicating over a DSPI link.
The actual minimum SCK cycle time is limited by pad performance.
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].
This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.
10
11
12
t
SUO
t
t
HO
Symbol
HI
CC
CC
CC
Master (MTFE = 0)
Slave
Master (MTFE = 1,
CPHA = 0)
Master (MTFE = 1,
CPHA = 1)
Master (MTFE = 0)
Slave
Master (MTFE = 1,
CPHA=0)
CPHA=1)
Master (MTFE = 0)
Slave
Master (MTFE = 1,
CPHA = 0)
Master (MTFE = 1,
CPHA = 1)
Master (MTFE = 1,
Characteristic
Preliminary—Subject to Change Without Notice
MPC5634M Microcontroller Data Sheet, Rev. 3
Table 31. DSPI Timing
7
Min.
5.5
45
-4
-4
-5
-5
7
8
40 MHz
Data Valid (after SCK edge)
Data Hold Time for Outputs
Data Hold Time for Inputs
Max.
25
45
1,2
6
6
(continued)
Min.
5.5
25
-4
-4
-5
-5
7
4
60 MHz
Max.
25
25
6
6
Min.
5.5
21
-4
-4
-5
-5
7
3
80 MHz
Freescale Semiconductor
Max.
25
21
6
6
Unit
ns
ns
ns

Related parts for mpc5632m