mpc5632m Freescale Semiconductor, Inc, mpc5632m Datasheet - Page 26

• Manufacturer Part Number: mpc5632m
• Description: Mpc5634m Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

Overview
1.3.18.1
The PIT provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. The PIT has
no external input or output pins and is intended to be used to provide system ‘tick’ signals to the operating system, as well as
periodic triggers for eQADC queues. Of the five channels in the PIT, four are clocked by the system clock, one is clocked by
the crystal clock. This one channel is also referred to as Real Time Interrupt (RTI) and is used to wakeup the device from low
power stop mode.
The following features are implemented in the PIT:
1.3.18.2
The System Timer Module (STM) is designed to implement the software task monitor as defined by AUTOSAR (see
http://www.autosar.org). It consists of a single 32-bit counter, clocked by the system clock, and four independent timer
comparators. These comparators produce a CPU interrupt when the timer exceeds the programmed value.
The following features are implemented in the STM:
1.3.19
The Software Watchdog Timer (SWT) is a second watchdog module to complement the standard Power Architecture watchdog
integrated in the CPU core. The SWT is a 32-bit modulus counter, clocked by the system clock or the crystal clock, that can
provide a system reset or interrupt request when the correct software key is not written within the required time window.
The following features are implemented:
1.3.20
The NPC (Nexus Port Controller) block provides real-time development support capabilities for the MPC5634M Power
Architecture-based MCU in compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied for
MCUs without requiring external address and data pins for internal visibility. The NPC block is an integration of several
individual Nexus blocks that are selected to provide the development support interface for the MPC5634M. The NPC block
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5 independent timer channels
Each channel includes 32-bit wide down counter with automatic reload
4 channels clocked from system clock
1 channel clocked from crystal clock (wake-up timer)
Wake-up timer remains active when System STOP mode is entered. Used to restart system clock after predefined
time-out period
Each channel can optionally generate an interrupt request or a trigger event (to trigger eQADC queues) when the timer
reaches zero
One 32-bit up counter with 8-bit prescaler
Four 32-bit compare channels
Independent interrupt source for each channel
Counter can be stopped in debug mode
32-bit modulus counter
Clocked by system clock or crystal clock
Optional programmable watchdog window mode
Can optionally cause system reset or interrupt request on timeout
Reset by writing a software key to memory mapped register
Enabled out of reset
Configuration is protected by a software key or a write-once register
Software Watchdog Timer (SWT)
Nexus Port Controller
Peripheral Interrupt Timer (PIT)
System Timer Module (STM)
Preliminary—Subject to Change Without Notice
MPC5634M Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor