mpc5534mzq66 Freescale Semiconductor, Inc, mpc5534mzq66 Datasheet - Page 20

• Manufacturer Part Number: mpc5534mzq66
• Description: Mpc5534 High Performance Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Electrical Characteristics
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
3.10
20
Num
Num
All internal registers retain data at 0 Hz.
Up to the maximum frequency rating of the device (see
“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.
Self clocked mode (SCM) frequency is the frequency that the PLL operates at when the reference frequency falls below f
This frequency is measured on the CLKOUT pin with the divider set to divide-by-2 of the system clock. NOTE: In SCM, the
MFD and PREDIV have no effect and the RFD is bypassed.
This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case,
V
This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case,
V
I
C
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time will also include the crystal
startup time.
PLL is operating in 1:1 PLL mode.
VDDE = 3.0 to 3.6V
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via V
for a given interval. CLKOUT divider set to divide-by-2.
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of jitter + Cmod.
Modulation depth selected must not result in f
f
Note that the ICO frequency may be higher than the maximum allowable system frequency, in that case, the FMPLL
Synthesizer Control Register Reduced Frequency Divider (FMPLL_SYNCR[RFD]) must be set to divide by 2 (RFD=0b001). In
other words, for a 40 MHz maximum device (system frequency), the FMPLL should be programmed to generate 80 MHz at the
ICO output and then divided by 2 by the RFD to provide the 40 MHz system clock.
20
21
22
xtal
sys
1
2
3
extal
xtal
PCB_EXTAL
= f
is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
– V
– V
ADC Clock (ADCLK) Frequency
Conversion Cycles
Stop Mode Recovery Time
ico
Frequency Modulation Range Limit
(f
ICO Frequency.
f
Predivider Output Frequency (to PLL)
extal
ico
Differential
Single Ended
sys
xtal
/ (2
eQADC Electrical Characteristics
=[f
Max must not be exceeded)
and C
>= 400mV criteria has to be met for oscillator’s comparator to produce output clock.
>= 400mV criteria has to be met for oscillator’s comparator to produce output clock.
RFD
ref
*(MFD+4)]/(PREDIV+1)
)
PCB_XTAL
Characteristic
Table 12. HiP7 FMPLL Electrical Specifications (continued)
Table 13. eQADC Conversion Specifications (Operating)
Characteristic
are the measured PCB stray capacitances on EXTAL and XTAL, respectively
(V
DDSYN
2
DDSYN
Preliminary—Subject to Change Without Notice
MPC5534 Microcontroller Data Sheet, Rev. 0
1
= 3.0V to 3.6 V, V
15
and V
14
sys
SSSYN
value greater than the f
and variation in crystal oscillator frequency increase the jitter percentage
Symbol
f
Table
PREDIV
C
SS
f
mod
ico
= V
1).
SSSYN
Symbol
F
ADCLK
T
CC
= 0 V, T
SR
sys
Value
maximum specified value.
Min.
0.8
48
4
A
13+2 (or 15)
14+2 (or 16)
= T
Min
L
10
1
to T
H
)
13+128 (or 141)
14+128 (or 142)
Freescale Semiconductor
Value
80
Max.
f
Max
2.4
MAX
12
—
16
sys
ADCLK
cycles
.
MHz
Unit
%f
MHz
MHz
Unit
µs
sys
LOR
.