tspc603r ATMEL Corporation, tspc603r Datasheet - Page 26
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tspc603r
Manufacturer Part Number
tspc603r
Description
Powerpc 603e Risc Microprocessor Family Pid7t-603e
Manufacturer
ATMEL Corporation
Datasheet
1.TSPC603R.pdf
(58 pages)
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Notes:
Figure 11-4. Output Timing Diagram
26
1. All output specifications are measured from the 1.4V of the rising edge of SYSCLK to the TTL level (0.8V or 2V) of the signal
2. All maximum timing specifications assume C
3. This minimum parameter assumes C
4. SYSCLK to output valid (5.5V to 0.8V) includes the extra delay associated with discharging the external voltage from 5.5V to
5. t
6. The output signal transitions from GND to 2V or V
7. The nominal precharge width for ABB and DBB is 0.5 × t
8. The nominal precharge width for ARTRY is 1 × t
TSPC603R
(Except TS, ABB,
in question. Both input and output timings are measured at the pin. See
0.8V instead of from V
plied by the period of SYSCLK to compute the actual time duration (ns) of the parameter in question.
sysclk
ALL OUTPUTS
DBB, ARTRY)
is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multi-
ABB, DBB
SYSCLK
ARTRY
TS
12
DD
to 0.8V (5V CMOS levels instead of 3.3V CMOS levels).
VM
14
13
L
= 0 pF.
VM = Midpoint Voltage (1.4V)
L
15
16
= 50 pF.
sysclk
DD
VM
to 0.8V.
.
sysclk
18
13
20
.
19
17
Figure
16
15
21
11-4.
VM
5410B–HIREL–09/05