tspc603r ATMEL Corporation, tspc603r Datasheet - Page 38

• Manufacturer Part Number: tspc603r
• Description: Powerpc 603e Risc Microprocessor Family Pid7t-603e
• Manufacturer: ATMEL Corporation

12.3.5
Table 12-2.
38
Exception Type
Reserved
System reset
Machine check
TSPC603R
PowerPC 603R Microprocessor Exception Model
Exceptions and Conditions
Vector Offset
00000
00100
00200
As specified by the PowerPC architecture, all 603R exceptions can be described as either pre-
cise or imprecise and either synchronous or asynchronous. Asynchronous exceptions (some of
which are maskable) are caused by events external to the processor’s execution; synchronous
exceptions, which are all handled precisely by the 603R, are caused by instructions. The 603R
exception classes are shown in
Table 12-1.
Although exceptions have other characteristics as well, such as whether they are maskable or
non-maskable, the distinctions shown in
603R handles uniquely. Note that
While the PowerPC architecture supports imprecise handling of floating-point exceptions, the
603R implements these exception modes as precise exceptions.
The 603R’s exceptions, and conditions that cause them, are listed in
are specific to the 603R are indicated.
(hex)
Synchronous/Asynchronous
Asynchronous, Non Maskable
Asynchronous, Maskable
Synchronous
• Synchronous, Imprecise – the PowerPC architecture defines two imprecise floating-point
• Asynchronous, Maskable – the external, SMI, and decrementer interrupts are maskable
• Asynchronous, Non-maskable – there are two non-maskable asynchronous exceptions:
exception modes, recoverable and nonrecoverable. Even though the 603R provides a means
to enable the imprecise modes, it implements these modes identically to the precise mode
(That is, all enabled floating-point exceptions are always precise on the 603R).
asynchronous exceptions. When these exceptions occur, their handling is postponed until the
next instruction, and any exceptions associated with that instruction completes execution. If
there are no instructions in the execution units, the exception is taken immediately upon
determination of the correct restart address (for loading SRR0).
the system reset and machine check exception. These exceptions may not be recoverable, or
may provide a limited degree of recoverability. All exceptions report recoverability through the
SMR[RI] bit.
Causing Conditions
–
A system reset is caused by the assertion of either SRESET or HRESET
A machine check is caused by the assertion of the TEA signal during a data bus
transaction, assertion of MCP, or an address or data parity error
PowerPC 603R Microprocessor Exception Classifications
Table
Table 12-1
Precise/Imprecise
Imprecise
Precise
Precise
12-1.
Table 12-1
includes no synchronous imprecise instructions.
define categories of exceptions that the
Instruction-caused exceptions
Exception Type
Machine check
System reset
External interrupt
Decrementer
System management interrupt
Table
12-2. Exceptions that
5410B–HIREL–09/05