dp83840a National Semiconductor Corporation, dp83840a Datasheet - Page 42

• Manufacturer Part Number: dp83840a
• Description: 10/100 Mb/s Ethernet Physical Layer
• Manufacturer: National Semiconductor Corporation

Version A
4.0 Registers
The MII supports up to 32 word-wide registers per addressable connected device. The DP83840A's register allocation is
as shown below. Each register is described in the Sections 4.2 to 4.17 that follow. Section 3.2 describes the MII serial
access control method.
4.1 KEY TO DEFAULTS
In the register descriptions that follow, the default column
takes the form
<reset value>, <access type>/<attribute(s)>
Where:
<reset value>:
00h
01h
02h
03h
04h
05h
06h
07h-0Fh
10h-11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh-1Fh
Address
(Pin #)
1
0
X
BMCR
BMSR
PHYIDR1
PHYIDR2
ANAR
ANLPAR
ANER
Reserved
Reserved
DCR
FCSCR
Reserved
RECR
SRR
PCR
LBREMR
PAR
Reserved
10BTSR
10BTCR
Reserved
Bit Set to Logic One
Bit Set to Logic Zero
No Default Value
Value Latched in from Pin # at Reset
Register Name
Basic Mode Control Register
Basic Mode Status Register
PHY Identifier Register #1
PHY Identifier Register #2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
Reserved for Future Assignments by the MII Working Group
Reserved for PHY Specific Future Assignments by Vendor
Disconnect Counter Register
False Carrier Sense Counter Register
Reserved--Do Not Read/Write to this Register
Receive Error Counter Register
Silicon Revision Register
PCS Sub-Layer Configuration Register
Loopback, Bypass and Receiver Error Mask Register
PHY Address Register
Reserved for PHY Specific Future Assignment by Vendor
10BASE-T Status Register
10BASE-T Configuration Register
Reserved for Future Use--Do Not Read/Write to These Registers
42
<access type>:
<attribute(s)>:
RO = Read Only
RW = Read/Write
L = Latching
SC = Self Clearing
P = Value Permanently Set
Description
National Semiconductor