dp83840a National Semiconductor Corporation, dp83840a Datasheet - Page 7

• Manufacturer Part Number: dp83840a
• Description: 10/100 Mb/s Ethernet Physical Layer
• Manufacturer: National Semiconductor Corporation

Version A
2.0 Pin Description
2.2 100 Mb/s SERIAL PMD INTERFACE
2.3 10 Mb/s INTERFACE
ENCSEL
(PHYAD[1])
LBEN
(PHYAD[0])
TD-
TD+
SD-
SD+
RD-
RD+
REQ
RTX
TXU-
TXU+
TXS-
TXS+
RXI-
RXI+
Signal Name
I = TTL/CMOS input
O (ECL)
I (ECL)
I (ECL)
I/O, J
I/O, J
Type
O
O
I
I
I
O = TTL/CMOS output
(Continued)
Pin #
53
49
16
17
29
28
25
26
23
24
20
21
7
8
6
5
ENCODE SELECT: Used to select binary or MLT-3 coding scheme in the PMD
transceiver (at the DP83223, logic high selects binary coding scheme and logic low
selects MLT-3 coding scheme).
This is also the PHY address sensing (PHYAD[1]) pin for multiple PHY applications-
-see Section 2.8 for more details.
LOOPBACK ENABLE: For 100BASE-TX operation, this pin should be connected
to the Loopback Enable pin of a DP83223 100 Mb/s Transceiver:
1 = local 100BASE-TX transceiver Loopback enabled
0 = local 100BASE-TX transceiver Loopback disabled (normal operation)
This is also the PHY address sensing (PHYAD[0]) pin for multiple PHY applications-
-see Section 2.8 for more details.
This pin has no effect during 10 Mb/s operation.
TRANSMIT DATA: Differential ECL 125 Mb/s serialized transmit data outputs to
the PMD transceiver (such as the DP83223).
SIGNAL DETECT: Differential ECL signal detect inputs. Indicates that the PMD
transceiver has detected a receive signal from the twisted pair or fiber media.
RECEIVE DATA: Differential ECL 125 Mb/s receive data inputs from the PMD
transceiver (such as the DP83223).
EQUALIZATION RESISTOR: A resistor connected between this pin and GND or
V
encoded transmit data (TXU+/- or TXS+/-). Typically no resistor is required for
operation with cable lengths less than 100m. Great care must be taken to ensure
system timing integrity when using cable lengths greater than 100m. Refer to the
IEEE 802.3u standard, Clause 29 for more details on system topology issues.
This value must be determined empirically. Refer to section 3.7.8 for further detail.
EXTENDED CABLE RESISTOR: A resistor connected between this pin and GND
or V
). Typically no resistor is required for operation with cable lengths less than 100m.
Great care must be taken to ensure system timing integrity when using cable
lengths greater than 100m. Refer to the IEEE 802.3u standard, Clause 29 for more
details on system topology issues.
This value must be determined empirically. Refer to section 3.7.8 for further detail.
UNSHIELDED TWISTED PAIR OUTPUT: This differential output pair sources the
10BASE-T transmit data and link pulses for UTP cable.
SHIELDED TWISTED PAIR OUTPUT: This differential output pair sources the
10BASE-T transmit data and link pulses for STP cable.
TWISTED PAIR RECEIVE INPUT: These are the differential 10BASE-T receive
data inputs for either STP or UTP.
CC
CC
adjusts the equalization step amplitude on the 10BASE-T Manchester
adjusts the amplitude of the differential transmit outputs (TXU+/- or TXS+/-
Z = TRI-STATE output
7
J = IEEE 1149.1 pin
Description
National Semiconductor