dp83222 National Semiconductor Corporation, dp83222 Datasheet
dp83222
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dp83222 Summary of contents
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... The DP83222 CYCLONE Stream Cipher Scrambler Descrambler Device is an integrated circuit designed to in- terface directly with the serial bit streams of a Twisted Pair FDDI PMD The DP83222 is designed to be fully compatible with the National Semiconductor FDDI Chip Sets including the DP83223 TWISTER ...
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... Figure 2 reveals a fairly elementary design The scrambler logic requires that the incoming data be NRZ for- matted which the DP83222 accomplishes via the input de- coder After being decoded to NRZ the data UD is routed to one input of the Exclusive OR gate XOR-A The other ...
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Functional Description 1 3 STREAM CIPHER (DATA DESCRAMBLING) The analysis of the Stream Cipher descrambler design is somewhat more complex than the scrambler circuit shown below The concept of the stream cipher is based upon hy- pothetical comparison ...
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Functional Description The result from XOR hypothetical data sequence HD that should match the original unscrambled NRZ IDLE data barring any noise events The Boolean progression in Figure 4 demonstrates that HD should equal the original ...
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... RXCO ENC0 9 ENC1 Pin Definitions and Connection Diagrams 28-Pin PLCC FIGURE 5 DP83222 Pinout TABLE I Pinout Summary Description V CC GND ECLV CC ECLGND External V CC Received Data from PMD Receiver 125 MHz Clock from Receiver PLL Transmit Data from PHY PMRD ...
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... DSCO g TTL compatible inputs These pins work in conjunction with one another to select different encoding schemes or to place the DP83222 device into transparent mode where no scram- bling or encoding occurs Refer to Ta- ble II for details of operation TTL compatible input data This input ...
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Electrical Characteristics 4 1 ABSOLUTE MAXIMUM RATINGS If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Logic Power ( Referenced to GND ECL Power (ECLV ...
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... Note 1 This parameter is not tested but is assured by correlation with characterization data Note 2 Data Valid and Hold Acquisition timing specifications are based on Transmit and Receive clocks of 125 MHz (8 ns period) and include finite asynchronous delay Note 3 The DP83222 is FDDI compliant and will perform to specification over typical Conditions Refer to Figure 8 ...
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... Transparent mode of operation refers to the ability of the DP83222 to pass a given datastream through without imposing any scrambling or descrambling on the data Data into Scrambler Data out of Scrambler also Data into Descrambler Descrambler 11885 – 7 FIGURE 11 ECL Transition Times ...
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TABLE III Clock Detect and Signal Detect Stream-Cipher Initialization refers to the algorithm employed by the Stream Cipher logic which by processing the encoded datastream ultimately enters the Hold state allowing for synchronized descrambling All ...
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... Italiano National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Order Number DP83222V NS Package Number V28A 2 A critical component is any component of a life ...