dp83222 National Semiconductor Corporation, dp83222 Datasheet - Page 4

• Manufacturer Part Number: dp83222
• Description: Cyclone Twisted Pair Fddi Stream Cipher Device
• Manufacturer: National Semiconductor Corporation

4 demonstrates that HD should equal the original unscram-
1 0 Functional Description
The result from XOR-D is a hypothetical data sequence HD
that should match the original unscrambled NRZ IDLE data
barring any noise events The Boolean progression in Figure
bled IDLE bits Over time Register H is loaded with the
hypothetical data sequence HD
Before the Line State Monitor detects a valid IDLE se-
quence (no less than 50 consecutive IDLE bits) the Stream
Cipher logic remains in the Sample mode While in Sample
mode the MUX select input ‘‘sel’’ routes the ‘‘in sample’’
input to Register B The MUX input ‘‘in sample’’ is con-
nected to the original SD datastream which continuously
loads and updates Register B so that its contents dynami-
cally match Register A This dynamic match is important as
it ensures synchronization with the LFSR in the scrambler
section
When the Line State Monitor logic within the Register H
block recognizes sufficient consecutive IDLE bits it will out-
put a Hold Flag HF which controls the MUX feeding Regis-
ter B When HF becomes true the MUX ‘‘in hold’’ input is
selected which routes the LDD data sequence back into
Register B This configures Register B and XOR-E into an
LFSR (identical to that in the scrambler logic in Section 1 2)
Register B now an LFSR is synchronized with the incoming
datastream SD allowing XOR-F to descramble SD by a
simple XOR function with LDD To ensure continuous syn-
chronization for valid conditions the Hold Timer in the Reg-
ister H block will hold HF true for a sufficient time until more
IDLE bits can be decoded which resets the timer The Hold
Since LDS n
Then SD
And Since UD n
Then SD n
Since SD n
And SD n
Then SD n
And Since SD n
Then HD n
If HF
And LDD n
And Since DD n
Then DD n
e
1
e
e
(UD n
e
e
e
e
e
e
e
due to the detection of sufficient valid IDLE symbols
(LDS n-9
FIGURE 4 Stream Cipher Boolean Analysis
LDS n
(SD n
UD n
LDS n
(LDS n-9
SD n-9
(LDS n-9
e
e
e
(Continued)
LDS n
1
(LDS n
LDS n )
SD n )
IDLE bits
SD n-11
LDS n-11 )
because LDD dynamically tracks LDS
LDS n-11 )
LDS n-11 )
SD)
e
e
(LDS n
4
(LDS n
e
Timer time-out period is based on the maximum time under
normal operation between IDLE occurrences (
If IDLE symbols cease to be decoded the Hold Timer will
time out forcing HF false This will cause the stream cipher
to fall into the sample mode again awaiting further valid line
states for resynchronization
This analysis is intended to provide a general understanding
of the mechanisms involved in the stream cipher process
Some circuit details were omitted for simplification A more
detailed logical and Boolean description of the stream ci-
pher process is generally available
1 4 STREAM CIPHER BOOLEAN
The following Boolean analysis supports the stream cipher
logic for IDLE reception example stated herein
Given that the character
tion
UD n
LDS n
SD n
SD n
HD n
HF
LDD n
DD n
LDS n
LDS n )
UD n
e
e
e
e
e
e
e
e
Unscrambled Data (‘‘IDLE’’ ones)
Scrambler’s LFSR feedback data (Pseudo Ran-
dom)
scrambled data (LDS n
result of XOR-C
Hypothetical Data (SD n
Hold Flag
Descrambler LFSR feedback data
Descrambled Data (SD n
e
LDS n )
1
IDLE bits
denotes an exclusive OR func-
UD n )
SD n )
LDD n )
l
722 ms)