dp83222 National Semiconductor Corporation, dp83222 Datasheet - Page 3

• Manufacturer Part Number: dp83222
• Description: Cyclone Twisted Pair Fddi Stream Cipher Device
• Manufacturer: National Semiconductor Corporation

1 0 Functional Description
1 3 STREAM CIPHER (DATA DESCRAMBLING)
The analysis of the Stream Cipher descrambler design is
somewhat more complex than the scrambler circuit shown
below The concept of the stream cipher is based upon hy-
pothetical comparison Because FDDI signalling includes
known line states comprised of unique 5-bit patterns it is
possible to utilize these patterns as comparison information
when analyzing the incoming scrambled datastream
Four FDDI line state patterns are commonly transmitted
within an FDDI ring during ring initialization and sustained
ring operation Three of these line state patterns HALT
MASTER and QUIET are used during PCM initialization and
ring fault indication The fourth pattern the IDLE is em-
ployed during PCM initialization and normal ring operation
The stream cipher operates in two modes Sample mode
and Hold mode While it is possible to become synchronized
in the Sample mode during the reception of HALT
FIGURE 3 Simplified Stream Cipher Descrambler Logic
(Continued)
3
MASTER or QUIET patterns synchronization is lost as soon
as anything other than these patterns are received It is only
the IDLE line state that allows synchronization and asser-
tion of the Hold mode The Hold mode allows fully synchro-
nized descrambling of all incoming data regardless of sym-
bol type The IDLE line state is both sufficient and required
for assertion of the Hold mode of synchronization due to
frequent interspersion among normal FDDI traffic such as
Tokens and Frames
The IDLE line state pattern will be analyzed for this exam-
ple The IDLE symbol pair in the NRZ 5B format becomes
ten ones or 11111 11111 The analysis begins by examining
the logic design provided in Figure 3 The NRZ scrambled
data SD is routed to Register A which is an 11-bit serial
shift register with taps at registers 9 and 11 Taps 9 and 11
are input to the XOR-C gate which outputs the SD data-
stream SD is connected to one input of XOR-D The other
input to XOR-D is the original SD datastream
TL F 11885 – 3