mpc2106bsg66 Freescale Semiconductor, Inc, mpc2106bsg66 Datasheet - Page 14

• Manufacturer Part Number: mpc2106bsg66
• Description: 512kb And 1mb Burstramtm Secondary Cache Modules For Powerpctm Prep/chrp Platforms
• Manufacturer: Freescale Semiconductor, Inc

MPC2105A•MPC2106A•MPC2105B•MPC2106B
14
TAG RAM MATCH CYCLE
TAG RAM RESET (TCLR) CYCLE
Clock High Write to MATCH Invalid
Clock High Read to MATCH Valid
Address Valid to MATCH Valid
MATCH Valid Hold from Address Change
TG Low to MATCH Invalid
TG High to MATCH Valid
TCLR Setup Time
TCLR Hold Time
Status Bit Reset Time
Status Bit Hold from TCLR Low
TCLR Low to MATCH Invalid
TCLR High to MATCH Valid
TCLR Low to TAG High–Z
TCLR High to TAG Active
STANDBY Setup to TCLR Low
TCLR High to TWE Low
OUTPUT
Z 0 = 50
(a)
V L = 1.5 V
Parameter
Parameter
50
OUTPUT
255
Figure 1. Test Loads
(b)
+5 V
480
5 pF
Symbol
Symbol
t GHMX
t RHWX
t KHML
t KHMV
t AVMV
t AXMX
t SHRS
t RSML
t RSMV
t RSQZ
t RSQX
t PDSR
t GLML
t SRST
t STC
t HTC
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the de-
vice point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.
The table of timing values shows either a
Min
Min
30
80
—
—
—
—
—
—
—
—
—
—
2
4
1
2
TIMING LIMITS
MOTOROLA FAST SRAM
Tag RAM
Tag RAM
Max
Max
100
100
10
10
—
—
—
60
—
10
10
—
—
7
7
8
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns