mpc2106bsg66 Freescale Semiconductor, Inc, mpc2106bsg66 Datasheet - Page 5

• Manufacturer Part Number: mpc2106bsg66
• Description: 512kb And 1mb Burstramtm Secondary Cache Modules For Powerpctm Prep/chrp Platforms
• Manufacturer: Freescale Semiconductor, Inc

PIN DESCRIPTIONS
MOTOROLA FAST SRAM
66, 67, 68, 69, 71, 72, 73, 74,
155, 156, 157, 158, 160, 161,
162, 163, 165, 166, 167, 169,
17, 19, 20, 22, 24, 25, 26, 27,
32, 33, 34, 37, 38, 39, 40, 43,
44, 45, 47, 49, 50, 52, 53, 54,
119, 120, 122, 123, 124, 127,
128, 129, 131, 133, 134, 136,
103, 105, 106, 108, 109, 111,
93, 94, 95, 96, 99, 100, 101,
1, 13, 29, 31, 41, 46, 55, 57,
4, 5, 6, 7, 10, 11, 12, 14, 16,
9, 15, 21, 28, 35, 42, 48, 58
76, 77, 78, 80, 81, 82, 83,
8, 23, 51, 61, 75, 97, 112,
18, 36, 84, 107, 125, 173
70, 79, 89, 90, 102, 114,
116, 121, 130, 135, 143,
145, 147, 159, 168, 178
30, 56, 115, 144, 146
126, 132, 138, 148
137, 139, 141, 142
98, 104, 110, 118,
Pin Locations
140, 150, 164
170, 171
153, 154
113, 117
63, 152
64, 65
59, 60
3, 92
151
149
172
177
176
175
174
62
88
86
91
85
87
2
CWE0 – CWE7
BURSTMODE
PD1/IDSDATA
CLK0 – CLK4
ADS0, ADS1
PD0/IDSCLK
DH0 – DH31
RESERVED
DL0 – DL31
DIRTYOUT
DP0 – DP7
STANDBY
PD2, PD3
CNTEN0,
A0 – A28
CNTEN1
DIRTYIN
VALIDIN
Symbol
MATCH
ADDR0
ADDR1
TCLR
CG0,
TWE
CG1
V CC
V DD
V SS
ALE
TG
Output
Output
Output
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
I/O
Address Inputs – (MSB:0, LSB:28).
Least significant address bit when asynchronous Data RAMs are used.
Next to least significant address bit when asynchronous Data RAMs are used.
Data RAM Address Strobe – For MPC2105A/B use ADS0 only. For
MPC2106A/B use ADS0, ADS1.
Data RAM Address Latch Enable – Use for asynchronous Data RAM only.
Burstmode. 0 = Linear, 1 = Interleaved.
Data RAM Output Enables – For MPC2105A/B use CG0 only. For
MPC2106A/B use CG0, CG1.
Clock Inputs – CLK2 is for Tag RAM, CLK0, 1, 3, and 4 are for Data RAMs only.
For MPC2106A/B use all the clocks. For MPC2105A/B use CLK0 – CLK2 only.
Data RAM Count Enables – For MPC2105A/B use CNTEN0 only. For
MPC2106A/B use CNTEN0, CNTEN1.
Data RAM Write Enables – (MSB:0, LSB:7).
High Data Bus – (MSB:0, LSB:31).
Dirty input bit.
Dirty output bit.
Low Data Bus – (MSB:0, LSB:31).
Data Parity Bits – (MSB:0, LSB:7)
Tag RAM active high match indication.
Presence detect bit 0/EEPROM serial clock. (EEPROM option only).
Presence detect bit 1/EEPROM serial data. (EEPROM option only).
Presence detect bits.
Reserved pin.
Standby pin. Reduces standby power consumption.
Tag RAM clear.
Tag RAM output enable.
Tag RAM write enable.
Tag RAM valid bit.
+ 5 V power supply. Must be connected.
+ 3.3 V power supply. Must be connected.
Ground.
MPC2105A•MPC2106A•MPC2105B•MPC2106B
Description
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