mpc2106bsg66 Freescale Semiconductor, Inc, mpc2106bsg66 Datasheet - Page 6

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mpc2106bsg66

Manufacturer Part Number
mpc2106bsg66
Description
512kb And 1mb Burstramtm Secondary Cache Modules For Powerpctm Prep/chrp Platforms
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MPC2105A•MPC2106A•MPC2105B•MPC2106B
6
DATA RAM MCM69F618A SYNCHRONOUS TRUTH TABLE
NOTES:
ASYNCHRONOUS TRUTH TABLE
NOTES:
ABSOLUTE MAXIMUM RATINGS
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
Power Supply Voltage
Voltage Relative to V SS
Output Current (per I/O)
Power Dissipation
Temperature Under Bias
Operating Temperature
Storage Temperature
STANDBY
1. X means Don’t Care.
2. All inputs except CG must meet set–up and hold times for the low–to–high transition of clock (CLK0 – CLK4).
3. Wait states are inserted by suspending burst.
1. X means Don’t Care.
2. For a write operation following a read operation, CG must be high before the input data
required set–up time and held high through the input data hold time.
H
L
L
X
X
X
X
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
Deselected
Operation
Read
Read
Write
ADSx
H
H
H
H
L
L
L
Rating
CNTENx
X
X
X
H
H
MPC2105A/B
MPC2106A/B
L
L
Data RAM
CG
H
L
X
X
(Voltages Referenced to V SS = 0 V)
(See Notes 1 and 2)
Tag
CWEx
X
H
H
H
L
L
L
V in , V out
Symbol
T bias
V CC
T stg
I out
P D
T A
Data Out (DQ0 – DQ8)
CLKx
High–Z — Data In
L–H
L–H
L–H
L–H
L–H
L–H
L–H
– 0.5 to V CC + 0.5
I/O Status
– 0.5 to + 7.0
– 55 to + 125
High–Z
High–Z
– 10 to + 85
0 to +70
Value
± 30
± 20
4.6
9.2
(See Notes 1, 2, and 3)
External Address
External Address
Current Address
Current Address
Address Used
Next Address
Next Address
Unit
mA
°C
°C
°C
W
V
V
N/A
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
ensure the output devices are in High–Z at
power up.
This device contains circuitry to protect the
This BiCMOS memory circuit has been
This device contains circuitry that will
Write Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
MOTOROLA FAST SRAM
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Deselected
Operation

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