mpc2002sg66 Freescale Semiconductor, Inc, mpc2002sg66 Datasheet - Page 5

• Manufacturer Part Number: mpc2002sg66
• Description: 256kb And 512kb Burstram Secondary Cache Module For Powerpc
• Manufacturer: Freescale Semiconductor, Inc

DQ9 – DQ17
DQ0 – DQ8
UW
LW
NOTE:
MOTOROLA FAST SRAM
A15 – A0
BAA
TSC
TSP
G
K
E
All registers are positive–edge triggered. The TSC or TSP signals control the duration of the burst and the start of the next
burst. When TSP is sampled low, any ongoing burst is interrupted and a read (independent of W and TSC) is performed
using the new external address. Alternatively, a TSP–initiated two cycle WRITE can be performed by asserting TSP and
a valid address on the first cycle, then negating both TSP and TSC and asserting LW and/or UW with valid data on the se-
cond cycle (see Single Write Cycle in WRITE CYCLES timing diagram).
When TSC is sampled low (and TSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on
W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After
the first cycle of the burst, BAA controls subsequent burst cycles. When BAA is sampled low, the internal address is ad-
vanced prior to the operation. When BAA is sampled high, the internal address is not advanced, thus inserting a wait state
into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST
SEQUENCE GRAPH. Write refers to either or both byte write enables (LW, UW).
EXTERNAL
ADDRESS
9
9
REGISTERS
ADDRESS
REGISTER
WRITE
NOTE: The external two values for A1 and A0
BURST SEQUENCE GRAPH
A1 , A0 =
REGISTER
ENABLE
BLOCK DIAGRAM
provide the starting point for the burst
sequence graph. The burst logic ad-
vances A1 and A0 as shown above.
1,1
16
1,0
0,0
LOAD
(See Note)
A1
BURST LOGIC
D1
COUNTER
0,1
BINARY
(See Note)
A0
D0
Q1
Q0
A15 – A2
A1
A0
INTERNAL
ADDRESS
16
9
REGISTERS
MPC2002 MPC2003
DATA–IN
18
9
MEMORY
64K x 18
ARRAY
OUTPUT
BUFFER
9
9
5