mpc2002sg66 Freescale Semiconductor, Inc, mpc2002sg66 Datasheet - Page 8

• Manufacturer Part Number: mpc2002sg66
• Description: 256kb And 512kb Burstram Secondary Cache Module For Powerpc
• Manufacturer: Freescale Semiconductor, Inc

MPC2002 MPC2003
8
Input Timing Measurement Reference Level
Input Pulse Levels
Input Rise/Fall Time
READ/WRITE CYCLE TIMING
NOTES:
Cycle Time
Clock Access Time
Output Enable to Output Valid
Clock High to Output Active
Clock High to Output Change
Output Enable to Output
Active
Output Disable to Q High–Z
Clock High to Q High–Z
Clock High Pulse Width
Clock Low Pulse Width
Setup Times:
Hold Times:
1. A read cycle is defined by UW and LW high or TSP low for the setup and hold times. A write cycle is defined by LW or UW low and TSP high
2. All read and write cycle timings are referenced from K or G.
3. G is a don’t care when UW or LW is sampled low.
4. Maximum access times are guaranteed for all possible PowerPC 60x external bus cycles.
5. Transition is measured 500 mV from steady–state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At any
6. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of clock (K) whenever TSP
for the setup and hold times.
given voltage and temperature, t KHQZ max is less than t KHQX1 min for a given device and from device to device.
or TSC are low and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of
K when the chip is selected.Chip enable must be valid at each rising edge of clock for the device (when TSP or TSC is low) to remain enabled.
OUTPUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1A
Z 0 = 50 Ω
Address Advance
Address Advance
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V CC = 5.0 V
(See Notes 1, 2, and 3) (W refers to either or both byte write enables)
Address Status
Address Status
Chip Select
Chip Select
Address
Address
Data In
Data In
. . . . . . . . . . . . . . .
Write
Write
V L = 1.5 V
R L = 50 Ω
5% T A = 0 to + 70 C, Unless Otherwise Noted)
t KHQX1
t KHQX2
t KHBAX
Symbol
t TSVKH
t BAVKH
t KHTSX
t WVKH
t KHWX
t KHKH
t KHQV
t GLQV
t GLQX
t GHQZ
t KHQZ
t DVKH
t KHDX
t KHKL
t KLKH
t AVKH
t EVKH
t KHAX
t KHEX
0 to 3.0 V
AC TEST LOADS
1.5 V
3 ns
MPC2002SG66/
MPC2003SG66
Min
2.5
0.5
15
—
—
—
6
3
0
2
5
5
Output Timing Reference Level
Output Load
Max
OUTPUT
—
—
—
—
—
—
—
—
9
5
6
6
255 Ω
MPC2002SG60/
MPC2003SG60
16.6
Min
. . . . . . . . . . . .
2.5
0.5
—
—
—
6
3
0
2
5
5
Figure 1B
Max
—
11
—
—
—
—
—
—
—
+ 5 V
5
6
6
See Figure 1A Unless Otherwise Noted
480 Ω
5 pF
. . . . . . . . . . . . . . . . . . . . . . . . . .
MPC2002SG50/
MPC2003SG50
Min
2.5
0.5
20
—
—
—
6
3
0
2
6
6
MOTOROLA FAST SRAM
Max
—
14
—
—
—
—
—
—
—
6
6
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1.5 V
4
5
5
6
6