lan9115 Standard Microsystems Corp., lan9115 Datasheet - Page 125
lan9115
Manufacturer Part Number
lan9115
Description
Lan9115 Highly Efficient Single-chip 10/100 Non-pci Ethernet Controller
Manufacturer
Standard Microsystems Corp.
Datasheet
1.LAN9115.pdf
(136 pages)
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9115
6.6
SYMBOL
t
cycle
t
t
t
t
t
t
asu
dsu
csh
csl
ah
dh
nCS, nWR
Data Bus
A[7:1]
PIO writes are used for all LAN9115 write cycles. PIO writes can be performed using Chip Select (nCS)
or Write Enable (nWR). Either or both of these control signals must go high between cycles for the
period specified.
Note: The “Data Bus” width is 16 bits
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either
PIO Writes
DESCRIPTION
Write Cycle Time
nCS, nWR Assertion Time
nCS, nWR Deassertion Time
Address Setup to nCS, nWR Assertion
Address Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
Figure 6.5 PIO Write Cycle Timing
Table 6.7 PIO Write Cycle Timing
DATASHEET
125
MIN
165
32
13
0
0
7
0
TYP
Revision 1.5 (07-11-08)
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns